Method of metal sputtering for integrated circuit metal routing

Abstract

A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.

1 . A method of metal sputtering, comprising the steps of: 
 providing a wafer holder within a chamber; the chamber having inner walls;    coating the wafer holder and the inner walls of the chamber with a seasoning layer; the seasoning layer being comprised of: 
 a) a material etchable in a metal barrier layer etch process; or  
 b) an insulating or non-conductive material;  
   placing a wafer upon the seasoning layer coated wafer holder; the wafer including two or more wafer conductive structures thereover;    cleaning the wafer wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures;    forming a metal barrier layer at least over the wafer and the wafer conductive structures;    removing the wafer from the chamber;    forming a patterned masking layer over the metal barrier layer, leaving first exposed portions of the metal barrier layer;    using the patterned masking layer as masks, forming at least two adjacent upper metal structures over the first exposed portions of the metal barrier layer;    removing the patterned masking layer exposing second exposed portions of the metal barrier layer adjacent the at least two adjacent upper metal structures; and    etching and removing the second exposed portions of the metal barrier layer from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process; the metal barrier layer etch process also etching and removing the exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.    
     
     
         2 - 66 . (canceled)  
     
     
         67 . A method of forming a device, comprising the steps of: 
 providing a wafer holder within a chamber; the chamber having inner walls;    coating the wafer holder and the inner walls of the chamber with a seasoning layer;    placing a wafer upon the seasoning layer coated wafer holder; the wafer including two or more wafer conductive structures thereover;    cleaning the wafer wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures; and    forming an upper metal structure at least over or between a set of the adjacent wafer conductive structures.    
     
     
         68 . The method of  claim 67 , wherein the seasoning layer is comprised of: 
 a) a material etchable in a metal barrier layer etch process; or    b) an insulating or non-conductive material.    
     
     
         69 . The method of  claim 67 , whereby the formation of the upper metal structure at least over or between a set of the adjacent wafer conductive structures includes the sequential steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned;    removing the wafer from the chamber;    forming a patterned masking layer over the metal barrier layer, leaving first exposed portions of the metal barrier layer;    using the patterned masking layer as masks, forming the upper metal structure over the first exposed portions of the metal barrier layer;    removing the patterned masking layer exposing second exposed portions of the metal barrier layer adjacent the upper metal structure; and    etching and removing the second exposed portions of the metal barrier layer from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process; the seasoning layer portions being comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material; the metal barrier layer etch process also etching and removing the exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.    
     
     
         70 . The method of  claim 67 , whereby the wafer includes a passivation layer formed under the two or more wafer conductive structures.  
     
     
         71 . The method of  claim 67 , further comprising the steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    forming a seed metal layer over the metal barrier layer.    
     
     
         72 . The method of  claim 67 , further comprising the steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    forming a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 500 to 8000 Å and being comprised of copper or gold.    
     
     
         73 . The method of  claim 67 , further comprising the steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    forming a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 800 to 6000  521  and being comprised of copper or gold.    
     
     
         74 . The method of  claim 67 , wherein the wafer holder is comprised of Cr, Fe, Ni, Mn or Mo  
     
     
         75 . The method of  claim 67 , wherein the wafer holder is comprised of Cr, Fe or Ni.  
     
     
         76 . The method of  claim 67 , wherein the seasoning layer is comprised of a material etchable in a metal barrier layer etch process.  
     
     
         77 . The method of  claim 67 , wherein the seasoning layer has a thickness of from about 500 to 50,000 Å.  
     
     
         78 . The method of  claim 67 , wherein the seasoning layer has a thickness of from about 1000 to 10,000 Å.  
     
     
         79 . The method of  claim 67 , wherein the seasoning layer is comprised of an insulating or non-conductive material.  
     
     
         80 . The method of  claim 67 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 10,000 Å.  
     
     
         81 . The method of  claim 67 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 3000 Å.  
     
     
         82 . The method of  claim 67 , wherein the wafer conductive structures are gold bumps and the seasoning layer is comprised of TiW.  
     
     
         83 . The method of  claim 67 , wherein the wafer conductive structures are solder bumps or copper interconnects and the seasoning layer is comprised of Ti.  
     
     
         84 . The method of  claim 67 , wherein the wafer is cleaned using an argon cleaning process.  
     
     
         85 . The method of  claim 69 , wherein the metal barrier layer has a thickness of from about 50 to 5000 Å.  
     
     
         86 . The method of  claim 69 , wherein the metal barrier layer has a thickness of from about 100 to 3000 Å.  
     
     
         87 . The method of  claim 67 , wherein the upper metal structure is comprised of Cu, Ni, Au, Au/TiW, Cu/Ti, Ni/Cu/Ti, Cu/Cr or Ni/Cu Cr.  
     
     
         88 . The method of  claim 67 , further comprising the step of forming an intermetal dielectric layer over the wafer and the two or more wafer conductive structures.  
     
     
         89 . The method of  claim 67 , wherein at least two adjacent upper metal structures are formed.  
     
     
         90 . The method of  claim 67 , wherein the seasoning layer is comprised of TiW or Ti.  
     
     
         91 . The method of  claim 67 , wherein the seasoning layer is comprised of silicon oxide, silicon nitride or alumina.  
     
     
         92 . The method of  claim 67 , wherein the seasoning layer is comprised of silicon oxide.  
     
     
         93 . The method of  claim 67 , wherein the wafer is cleaned using an argon sputter cleaning process.  
     
     
         94 . A method of forming a device, comprising the steps of: 
 providing a wafer holder within a chamber; the chamber having inner walls;    coating the wafer holder and the inner walls of the chamber with a seasoning layer; the seasoning layer being comprised of: 
 a) a material etchable in a metal barrier layer etch process; or  
 b) an insulating or non-conductive material;  
   placing a wafer upon the seasoning layer coated wafer holder; the wafer including two or more wafer conductive structures thereover;    cleaning the wafer wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures; and    forming an upper metal structure at least over or between a set of the adjacent wafer conductive structures.    
     
     
         95 . The method of  claim 94 , whereby the formation of the upper metal structure at least over or between a set of the adjacent wafer conductive structures includes the sequential steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned;    removing the wafer from the chamber;    forming a patterned masking layer over the metal barrier layer, leaving first exposed portions of the metal barrier layer;    using the patterned masking layer as masks, forming the upper metal structure over the first exposed portions of the metal barrier layer;    removing the patterned masking layer exposing second exposed portions of the metal barrier layer adjacent the upper metal structure; and    etching and removing the second exposed portions of the metal barrier layer from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process; the seasoning layer portions being comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material; the metal barrier layer etch process also etching and removing the exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.    
     
     
         96 . The method of  claim 94 , whereby the wafer includes a passivation layer formed under the two or more wafer conductive structures.  
     
     
         97 . The method of  claim 94 , further comprising the steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    forming a seed metal layer over the metal barrier layer.    
     
     
         98 . The method of  claim 94 , further comprising the steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    forming a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 500 to 8000 Å and being comprised of copper or gold.    
     
     
         99 . The method of  claim 94 , further comprising the steps of: 
 forming a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    forming a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 800 to 6000 Å and being comprised of copper or gold.    
     
     
         100 . The method of  claim 94 , wherein the wafer holder is comprised of Cr, Fe, Ni, Mn or Mo  
     
     
         101 . The method of  claim 94 , wherein the wafer holder is comprised of Cr, Fe or Ni.  
     
     
         102 . The method of  claim 94 , wherein the seasoning layer is comprised of a material etchable in a metal barrier layer etch process.  
     
     
         103 . The method of  claim 94 , wherein the seasoning layer has a thickness of from about 500 to 50,000 Å.  
     
     
         104 . The method of  claim 94 , wherein the seasoning layer has a thickness of from about 1000 to 10,000 Å.  
     
     
         105 . The method of  claim 94 , wherein the seasoning layer is comprised of an insulating or non-conductive material.  
     
     
         106 . The method of  claim 94 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 10,000 Å.  
     
     
         107 . The method of  claim 94 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 3000 Å.  
     
     
         108 . The method of  claim 94 , wherein the wafer conductive structures are gold bumps and the seasoning layer is comprised of TiW.  
     
     
         109 . The method of  claim 94 , wherein the wafer conductive structures are solder bumps or copper interconnects and the seasoning layer is comprised of Ti.  
     
     
         110 . The method of  claim 94 , wherein the wafer is cleaned using an argon cleaning process.  
     
     
         111 . The method of  claim 95 , wherein the metal barrier layer has a thickness of from about 50 to b  5000  Å.  
     
     
         112 . The method of  claim 95 , wherein the metal barrier layer has a thickness of from about 100 to 3000 Å.  
     
     
         113 . The method of  claim 94 , wherein the upper metal structure is comprised of Cu, Ni, Au, Au/TiW, Cu/Ti, Ni/Cu/Ti, Cu/Cr or Ni/Cu Cr.  
     
     
         114 . The method of  claim 94 , further comprising the step of forming an intermetal dielectric layer over the wafer and the two or more wafer conductive structures.  
     
     
         115 . The method of  claim 94 , wherein at least two adjacent upper metal structures are formed.  
     
     
         116 . The method of  claim 94 , wherein the seasoning layer is comprised of TiW or Ti.  
     
     
         117 . The method of  claim 94 , wherein the seasoning layer is comprised of silicon oxide, silicon nitride or alumina.  
     
     
         118 . The method of  claim 94 , wherein the seasoning layer is comprised of silicon oxide.  
     
     
         119 . The method of  claim 94 , wherein the wafer is cleaned using an argon sputter cleaning process.  
     
     
         120 . A structure, comprising: 
 a wafer holder having an overlying seasoning layer;    a cleaned wafer upon the seasoning layer coated wafer holder; the wafer including two or more wafer conductive structures thereover;    the cleaned wafer having re-deposited seasoning layer portions upon the wafer over and between adjacent wafer conductive structures; and    an upper metal structure at least over or between a set of the adjacent wafer conductive structures.    
     
     
         121 . The structure of  claim 120 , wherein the seasoning layer is comprised of: 
 a) a material etchable in a metal barrier layer etch process; or    b) an insulating or non-conductive material.    
     
     
         122 . The structure of  claim 120 , whereby the wafer includes a passivation layer formed under the two or more wafer conductive structures.  
     
     
         123 . The structure of  claim 120 , further comprising a metal barrier layer at least over the wafer and the wafer conductive structures.  
     
     
         124 . The structure of  claim 120 , further comprising: 
 a metal barrier layer at least over the wafer and the wafer conductive structures; and    a seed metal layer over the metal barrier layer.    
     
     
         125 . The structure of  claim 120 , further comprising: 
 a metal barrier layer at least over the wafer and the wafer conductive structures; and    a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 500 to 8000 Å and being comprised of copper or gold.    
     
     
         126 . The structure of  claim 120 , further comprising: 
 a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 800 to 6000  521  and being comprised of copper or gold.    
     
     
         127 . The structure of  claim 120 , wherein the wafer holder is comprised of Cr, Fe, Ni, Mn or Mo  
     
     
         128 . The structure of  claim 120 , wherein the wafer holder is comprised of Cr, Fe or Ni.  
     
     
         129 . The structure of  claim 120 , wherein the seasoning layer is comprised of a material etchable in a metal barrier layer etch process.  
     
     
         130 . The structure of  claim 120 , wherein the seasoning layer has a thickness of from about 500 to 50,000 Å.  
     
     
         131 . The structure of  claim 120 , wherein the seasoning layer has a thickness of from about 1000 to 10,000 Å.  
     
     
         132 . The structure of  claim 120 , wherein the seasoning layer is comprised of an insulating or non-conductive material.  
     
     
         133 . The structure of  claim 120 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 10,000 Å.  
     
     
         134 . The structure of  claim 120 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 3000 Å.  
     
     
         135 . The structure of  claim 120 , wherein the wafer conductive structures are gold bumps and the seasoning layer is comprised of TiW.  
     
     
         136 . The structure of  claim 120 , wherein the wafer conductive structures are solder bumps or copper interconnects and the seasoning layer is comprised of Ti.  
     
     
         137 . The structure of  claim 123 , wherein the metal barrier layer has a thickness of from about 50 to 5000 Å.  
     
     
         138 . The structure of  claim 123 , wherein the metal barrier layer has a thickness of from about 100 to 3000 Å.  
     
     
         139 . The structure of  claim 120 , wherein the upper metal structure is comprised of Cu, Ni, Au, Au/TiW, Cu/Ti, Ni/Cu/Ti, Cu/Cr or Ni/Cu Cr.  
     
     
         140 . The structure of  claim 120 , further comprising an intermetal dielectric layer over the wafer and the two or more wafer conductive structures.  
     
     
         141 . The structure of  claim 120 , wherein there are at least two adjacent upper metal structures.  
     
     
         142 . The structure of  claim 120 , wherein the seasoning layer is comprised of TiW or Ti.  
     
     
         143 . The structure of  claim 120 , wherein the seasoning layer is comprised of silicon oxide, silicon nitride or alumina.  
     
     
         144 . The structure of  claim 120 , wherein the seasoning layer is comprised of silicon oxide.  
     
     
         145 . A structure, comprising: 
 a wafer holder having an overlying seasoning layer;    a cleaned wafer upon the seasoning layer coated wafer holder; the wafer including two or more wafer conductive structures thereover; the seasoning layer being comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material;    the cleaned wafer having re-deposited seasoning layer portions upon the wafer over and between adjacent wafer conductive structures; and    an upper metal structure at least over or between a set of the adjacent wafer conductive structures.    
     
     
         146 . The structure of  claim 145 , whereby the wafer includes a passivation layer formed under the two or more wafer conductive structures.  
     
     
         147 . The structure of  claim 145 , further comprising a metal barrier layer at least over the wafer and the wafer conductive structures.  
     
     
         148 . The structure of  claim 145 , further comprising: 
 a metal barrier layer at least over the wafer and the wafer conductive structures; and    a seed metal layer over the metal barrier layer.    
     
     
         149 . The structure of  claim 145 , further comprising: 
 a metal barrier layer at least over the wafer and the wafer conductive structures; and    a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 500 to 8000 Å and being comprised of copper or gold.    
     
     
         150 . The structure of  claim 145 , further comprising: 
 a metal barrier layer at least over the wafer and the wafer conductive structures after the wafer is cleaned; and    a seed metal layer over the metal barrier layer; the seed metal layer having a thickness of from about 800 to 6000 Å and being comprised of copper or gold.    
     
     
         151 . The structure of  claim 145 , wherein the wafer holder is comprised of Cr, Fe, Ni, Mn or Mo  
     
     
         152 . The structure of  claim 145 , wherein the wafer holder is comprised of Cr, Fe or Ni.  
     
     
         153 . The structure of  claim 145 , wherein the seasoning layer is comprised of a material etchable in a metal barrier layer etch process.  
     
     
         154 . The structure of  claim 145 , wherein the seasoning layer has a thickness of from about 500 to 50,000 Å.  
     
     
         155 . The structure of  claim 145 , wherein the seasoning layer has a thickness of from about 1000 to 10,000 Å.  
     
     
         156 . The structure of  claim 145 , wherein the seasoning layer is comprised of an insulating or non-conductive material.  
     
     
         157 . The structure of  claim 145 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 10,000 Å.  
     
     
         158 . The structure of  claim 145 , wherein the seasoning layer is comprised of an insulating or non-conductive material and has a thickness of from about 500 to 3000 Å.  
     
     
         159 . The structure of  claim 145 , wherein the wafer conductive structures are gold bumps and the seasoning layer is comprised of TiW.  
     
     
         160 . The structure of  claim 145 , wherein the wafer conductive structures are solder bumps or copper interconnects and the seasoning layer is comprised of Ti.  
     
     
         161 . The structure of  claim 147 , wherein the metal barrier layer has a thickness of from about 50 to 5000 Å.  
     
     
         162 . The structure of  claim 147 , wherein the metal barrier layer has a thickness of from about 100 to 3000 Å.  
     
     
         163 . The structure of  claim 145 , wherein the upper metal structure is comprised of Cu, Ni, Au, Au/TiW, Cu/Ti, Ni/Cu/Ti, Cu/Cr or Ni/Cu Cr.  
     
     
         164 . The structure of  claim 145 , further comprising an intermetal dielectric layer over the wafer and the two or more wafer conductive structures.  
     
     
         165 . The structure of  claim 145 , wherein there are at least two adjacent upper metal structures.  
     
     
         166 . The structure of  claim 145 , wherein the seasoning layer is comprised of TiW or Ti.  
     
     
         167 . The structure of  claim 145 , wherein the seasoning layer is comprised of silicon oxide, silicon nitride or alumina.  
     
     
         168 . The structure of  claim 145 , wherein the seasoning layer is comprised of silicon oxide.