Universal test interface between a device under test and a test head

Abstract

In order to form a modular interface between a DUT board, which is housing devices under tests (DUT), to cables connected to a test head, a board spacer is provided that has an array of connectors. Each cable is connected to a respective connector, and the DUT board contains a corresponding array of connection points which are less than or equal to the number of connectors in the arrays on the board spacer. In this way, a common board spacer can be used to connect the cables to DUT boards housing different types of DUTs since the location of the connection points on the board spacer is known and kept constant. This interface allows a high speed and high fidelity connection between the test head and the devices on the DUTs for frequencies in excess of 50 MHz.

1 . An interface to perform high-parallelism testing of memory devices, comprising: 
 a first board holding one of the memory devices and having a receptacle connected to the one memory device; and    a plug connected to respective cables and to the receptacle to create a communication pathway,    wherein combinations of said first boards and said plugs allow high-parallelism testing of the memory devices.    
   
   
       2 . The interface of  claim 1 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test thirty-two (32) or more memory devices in the spacing frame.  
   
   
       3 . The interface of  claim 1 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test sixty-four (64) or more memory devices in the spacing frame.  
   
   
       4 . The interface of  claim 1 , wherein said first board holds only an additional receptacle, which is connected to an addition plug connected to additional respective cables to create an additional communication pathway.  
   
   
       5 . The interface of  claim 4 , wherein the receptacles on said first board are parallel with each other.  
   
   
       6 . The interface of  claim 5 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test thirty-two (32) or more memory devices in the spacing frame.  
   
   
       7 . The interface of  claim 5 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test sixty-four (64) or more memory devices in the spacing frame.  
   
   
       8 . The interface of  claim 7 , wherein each connection formed between respective pairs of receptacles and plugs forms a communication pathway for signals having a frequency of at least 50 MHz.  
   
   
       9 . A method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices, comprising: 
 unplugging first DUT boards from plugs, where each first DUT board has a first receptacle that is connected to a first memory device and each plug is connected to respective cables; and    plugging second DUT boards into the plugs, where each second DUT board has a second receptacle that is connected to a second memory device so as to form communication pathways between the cables and the second memory device,    wherein the combined second DUT boards and plugs allows high-parallelism testing of the second memory devices.    
   
   
       10 . The method of  claim 9 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test thirty-two (32) or more memory devices in the spacing frame.  
   
   
       11 . The method of  claim 9 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test sixty-four (64) or more memory devices in the spacing frame.  
   
   
       12 . The method of  claim 10 , wherein the second DUT board holds only an additional receptacle that is also connected to the second memory device, and further comprising connecting the additional receptacle to an addition plug that is connected to additional respective cables to create additional communication pathways.  
   
   
       13 . The method of  claim 12 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test thirty-two (32) or more memory devices in the spacing frame.  
   
   
       14 . The method of  claim 12 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test sixty-four (64) or more memory devices in the spacing frame.  
   
   
       15 . The interface of  claim 14 , wherein each connection formed between pairs of respective plugs and second or additional receptacles forms communication pathways for signals having a frequency of at least 50 MHz.