Method and process to make multiple-threshold metal gates CMOS technology

Abstract

Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

1 - 27 . (canceled)  
   
   
       28 . A CMOS device comprising 
 a Si-containing layer having source/drain regions present therein;    a gate dielectric present atop portions of said Si-containing layer; and    at least one alloy silicide metal gate located atop said gate dielectric, said alloy silicide metal gate is comprised of a metal bilayer or a metal alloy layer.    
   
   
       29 . The CMOS device of  claim 28  wherein said metal bilayer comprises a first metal and a second metal, said metals having different Fermi levels.  
   
   
       30 . The CMOS device of  claim 29  wherein said first metal comprises Co, Ni, Ti, W, Mo or Ta.  
   
   
       31 . The CMOS device of  claim 29  wherein said second metal comprises Co, Ni, Ti, W, Mo or Ta.  
   
   
       32 . The CMOS device of  claim 29  wherein said first metal is Co and said second metal is Ni.  
   
   
       33 . The CMOS device of  claim 28  wherein said metal alloy layer comprises a metal and an alloying additive.  
   
   
       34 . The CMOS device of  claim 33  wherein said metal of said metal alloy layer comprises Co, Ni, Ti, W, Mo or Ta.  
   
   
       35 . The CMOS device of  claim 33  wherein said alloying additive comprises C, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Hf, Ta, W, Re, Ir, Pt, or mixtures thereof, with the proviso that the alloy additive is not the same as the metal.  
   
   
       36 . The CMOS device of  claim 35  wherein said alloying additive comprises Al, Ti, V, Ge, Zr, Nb, Ru, Rh, Ag, In, Sn, Ta, Re, Ir, or Pt.  
   
   
       37 . The CMOS device of  claim 33  wherein said metal alloy layer contains from about 0.1 to about 50 atomic % of said alloying additive.