Inventor · disambiguated record
Diane C. Boyd
Also filed as: BOYD DIANE C · BOYD DIANE CATHERINE
35 granted patents·4 pending applications·1,771 citations·filing 1998–2008
98Inventor score
Files withIBM35BOYD DIANE C1DORIS BRUCE B1INTERNAITONAL BUSINESS MACHINE1INTERNAT BUSINSESS MACHINES CO1
Top patents by PatentIndex Score
39 records- 0198US7250658B2Hybrid planar and FinFET CMOS devicesIBM·Filed 2005·Granted Jul 31, 2007·164 cites·6 claims
- 0298US6271094B1Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitanceIBM·Filed 2000·Granted Aug 7, 2001·245 cites·31 claims
- 0397US7002214B1Ultra-thin body super-steep retrograde well (SSRW) FET devicesIBM·Filed 2004·Granted Feb 21, 2006·160 cites·20 claims
- 0497US6916698B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2004·Granted Jul 12, 2005·139 cites·8 claims
- 0597US6660598B2Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel regionIBM·Filed 2002·Granted Dec 9, 2003·137 cites·10 claims
- 0695US6911383B2Hybrid planar and finFET CMOS devicesIBM·Filed 2003·Granted Jun 28, 2005·109 cites·11 claims
- 0794US6846734B2Method and process to make multiple-threshold metal gates CMOS technologyIBM·Filed 2002·Granted Jan 25, 2005·105 cites·27 claims
- 0894US6841831B2Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate processIBM·Filed 2003·Granted Jan 11, 2005·74 cites·10 claims
- 0993US6762469B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2002·Granted Jul 13, 2004·68 cites·5 claims
- 1091US6221562B1Resist image reversal by means of spun-on-glassIBM·Filed 1998·Granted Apr 24, 2001·113 cites·1 claims
- 1190US6245619B1Disposable-spacer damascene-gate process for SUB 0.05 μm MOS devicesIBM·Filed 2000·Granted Jun 12, 2001·51 cites·8 claims
- 1289US6440808B1Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-polyIBM·Filed 2000·Granted Aug 27, 2002·48 cites·20 claims
- 1389US6353249B1MOSFET with high dielectric constant gate insulator and minimum overlap capacitanceINTERNAT BUSINSESS MACHINES CO·Filed 2001·Granted Mar 5, 2002·55 cites·10 claims
- 1488US7202516B2CMOS transistor structure including film having reduced stress by exposure to atomic oxygenIBM·Filed 2005·Granted Apr 10, 2007·12 cites·9 claims
- 1584US7602021B2Method and structure for strained FinFET devicesIBM·Filed 2007·Granted Oct 13, 2009·8 cites·2 claims
- 1684US6982196B2Oxidation method for altering a film structure and CMOS transistor structure formed therewithIBM·Filed 2003·Granted Jan 3, 2006·27 cites·13 claims
- 1783US7056782B2CMOS silicide metal gate integrationIBM·Filed 2004·Granted Jun 6, 2006·25 cites·19 claims
- 1883US6835633B2SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layerIBM·Filed 2002·Granted Dec 28, 2004·24 cites·7 claims
- 1981US7411227B2CMOS silicide metal gate integrationIBM·Filed 2006·Granted Aug 12, 2008·7 cites·16 claims
- 2081US7247569B2Ultra-thin Si MOSFET device structure and method of manufactureIBM·Filed 2003·Granted Jul 24, 2007·20 cites·26 claims
- 2177US7396747B2Hetero-integrated strained silicon n- and p-MOSFETsIBM·Filed 2007·Granted Jul 8, 2008·4 cites·3 claims
- 2276US6143635AField effect transistors with improved implants and method for making such transistorsIBM·Filed 1999·Granted Nov 7, 2000·37 cites·29 claims
- 2375US6040214AMethod for making field effect transistors having sub-lithographic gates with vertical side wallsIBM·Filed 1998·Granted Mar 21, 2000·47 cites·29 claims
- 2474US7655557B2CMOS silicide metal gate integrationIBM·Filed 2008·Granted Feb 2, 2010·4 cites·9 claims
- 2567US7075150B2Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene techniqueIBM·Filed 2003·Granted Jul 11, 2006·10 cites·15 claims
- 2667US6461529B1Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch schemeIBM·Filed 1999·Granted Oct 8, 2002·34 cites·4 claims
- 2764US7488658B2Stressed semiconductor device structures having granular semiconductor materialIBM·Filed 2006·Granted Feb 10, 2009·1 cites·8 claims
- 2864US7122849B2Stressed semiconductor device structures having granular semiconductor materialIBM·Filed 2003·Granted Oct 17, 2006·7 cites·7 claims
- 2963US6014422AMethod for varying x-ray hybrid resist space dimensionsINTERNAITONAL BUSINESS MACHINE·Filed 1998·Granted Jan 11, 2000·21 cites·17 claims
- 3060US7741166B2Oxidation method for altering a film structureIBM·Filed 2005·Granted Jun 22, 2010·1 cites·15 claims
- 3156US2008251813A1HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETSIBM·Filed 2008·Application pending·0 cites
- 3255US7273800B2Hetero-integrated strained silicon n- and p-MOSFETsIBM·Filed 2004·Granted Sep 25, 2007·3 cites·28 claims
- 3353US8669145B2Method and structure for strained FinFET devicesDORIS BRUCE B·Filed 2004·Granted Mar 11, 2014·4 cites·19 claims
- 3452US2007228473A1ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTUREIBM·Filed 2007·Application pending·0 cites
- 3551US7166521B2SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layerIBM·Filed 2004·Granted Jan 23, 2007·2 cites·17 claims
- 3648US7482243B2Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene techniqueIBM·Filed 2006·Granted Jan 27, 2009·0 cites·17 claims
- 3738US6593617B1Field effect transistors with vertical gate side walls and method for making such transistorsIBM·Filed 1998·Granted Jul 15, 2003·5 cites·13 claims
- 3838US2005106788A1Method and process to make multiple-threshold metal gates CMOS technologyIBM·Filed 2004·Application pending·0 cites
- 3937US2007001223A1Ultrathin-body schottky contact MOSFETBOYD DIANE C·Filed 2005·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Diane C. Boyd files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →