HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS

Abstract

The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

1 . A semiconductor structure comprising:
 a Si-containing substrate having platelets and dislocation loops present therein;   at least one region of substantially relaxed SiGe located on a portion of said Si-containing substrate, said substantially relaxed SiGe is positioned atop said platelets and said dislocation loops; and   at least one region of a strained semiconductor located on said substantially relaxed SiGe.   
     
     
         2 . The semiconductor structure of  claim 1  wherein said Si-containing substrate comprises Si, SiGe, SiC, SiGeC, a silicon-on-insulator or a silicon germanium-on-insulator. 
     
     
         3 . The semiconductor structure of  claim 1  wherein said platelets and dislocation loops are located within isolated regions of said Si-containing substrate. 
     
     
         4 . The semiconductor structure of  claim 1  wherein said at least one region of substantially relaxed SiGe is abutted by a strained SiGe region. 
     
     
         5 . The semiconductor structure of  claim 4  wherein said strained semiconductor is abutted by unstrained semiconductor, said unstrained semiconductor is located atop said strained SiGe region. 
     
     
         6 . The semiconductor structure of  claim 1  wherein said strained semiconductor comprises Si, SiGe, Ge, SiC, SiGeC or multilayers thereof. 
     
     
         7 . The semiconductor structure of  claim 1  wherein said strained semiconductor comprises Si having biaxial tensile strain. 
     
     
         8 . The semiconductor structure of  claim 1  wherein said SiGe alloy is a Si 1-x Ge x  composition in which x the mole fraction of Ge is uniform and is from about 0.01 to less than about 1. 
     
     
         9 . The semiconductor structure of  claim 1  wherein said SiGe alloy is a Si 1-x Ge x  composition that is graded wherein x increases from 0 at said surface of said Si-containing substrate to high values from about 0.01 to less than about 1 at upper region of the SiGe alloy. 
     
     
         10 . The semiconductor structure of  claim 1  further comprising at least one metal oxide semiconductor field effect transistor (MOSFET). 
     
     
         11 . The semiconductor structure of  claim 10  wherein said at least one MOSFET is a n-MOSFET that is located atop said strained semiconductor having biaxial tensile strain. 
     
     
         12 . The semiconductor structure of  claim 10  wherein said at least one MOSFFET comprises a p-MOSFET and a n-MOSFET, said p-MOSFET are located atop unstrained semiconductor that abuts said strained semiconductor, and said n-MOSFET is located atop said strained semiconductor. 
     
     
         13 . The semiconductor structure of  claim 10  wherein said at least one MOSFET comprises a p-MOSFET and a n-MOSFET, said p-MOSFET are located atop exposed strained SiGe alloy that abuts said substantially relaxed SiGe, and said n-MOSFET is located atop said strained semiconductor. 
     
     
         14 . The semiconductor structure of  claim 10  wherein said at least one MOSFET comprises a p-MOSFET and a n-MOSFET, said p-MOSFET are located atop exposed portions of said Si-containing substrate, and said n-MOSFET is located atop said strained semiconductor.