ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE

Abstract

The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

1 . A thin channel MOSFET comprising: 
 a SOI substrate comprising a SOI layer overlying a uniform insulator layer, said SOI layer having a lesser thickness portion and a greater thickness portion;    a gate region atop said SOI substrate having composite spacers;    source and drain extension regions within said greater thickness portion of said SOI layer;    a channel self-aligned to said gate region and separating said source and drain extension regions, said channel located in said lesser thickness region of said SOI layer; and    a localized oxide region atop said uniform insulator layer and underlying said channel region.    
   
   
       2 . The thin channel MOSFET of  claim 1 , wherein said composite spacer comprises a nitride spacer overlying a pad oxide spacer.  
   
   
       3 . The thin channel MOSFET of  claim 1 , having an external resistance of less than about 400.0 Ohm/μm.  
   
   
       4 . A thin channel MOSFET comprising: 
 a SOI substrate comprising a SOI layer and a uniform insulator layer, wherein said SOI layer is located directly on and above said uniform insulator layer;    a localized oxide region located with said SOI layer and vertically abutting said uniform insulator layer;    a device channel region located with said SOI layer and vertically abutting said localized oxide region;    a gate dielectric vertically abutting said device channel region; and    a functioning gate vertically abutting said device channel region, wherein said localized oxide region is self-aligned to said functioning gate, and wherein said device channel region is self-aligned to said functioning gate.    
   
   
       5 . The thin channel MOSFET of  claim 4 , further comprising a source extension region and a drain extension region that are separated by said device channel region.  
   
   
       6 . The thin channel MOSFET of  claim 4 , wherein said gate dielectric comprises one of SiO 2 , Si 3 N 4 , SiON, TiO 2 , Al 2 O 3 , ZrO 2 , HfO 2 , Ta 2 O 5 , La 2 O 3 , and perovskite-type oxides.  
   
   
       7 . The thin channel MOSFET of  claim 4 , wherein said device channel region has edges substantially self-aligned to edges of said functioning gate.  
   
   
       8 . The thin channel MOSFET of  claim 4 , further comprising at least one spacer located on sidewalls of said functioning gate.  
   
   
       9 . The thin channel MOSFET of  claim 8 , wherein said at least one spacer is a composite spacer comprising a nitride spacer overlying a pad oxide spacer.  
   
   
       10 . The thin channel MOSFET of  claim 4 , having an external resistance of less than about 400.0 Ohm/μm.  
   
   
       11 . The thin channel MOSFET of  claim 4 , wherein said SOI layer has a thickness ranging from about 20.0 nm to about 70.0 nm.  
   
   
       12 . The thin channel MOSFET of  claim 4 , wherein said SOI layer further comprises isolation regions.  
   
   
       13 . The thin channel MOSFET of  claim 4 , wherein said SOI layer comprises a material selected from Si, SiGe, SiGeC, SiC and combinations thereof.  
   
   
       14 . The thin channel MOSFET of  claim 4 , wherein said device channel region has a thickness less than about 50.0 nm.  
   
   
       15 . The thin channel MOSFET of  claim 14 , wherein said device channel region has a thickness from about 3.0 nm to about 30.0 nm.  
   
   
       16 . The thin channel MOSFET of  claim 4 , wherein said gate dielectric comprises thermal silicon oxide.  
   
   
       17 . The thin channel MOSFET of  claim 4 , where said gate conductor material comprises polysilicon.  
   
   
       18 . The thin channel MOSFET of  claim 4 , further comprising source/drain extension regions doped with a group III-A dopant or a group V dopant.  
   
   
       19 . The thin channel MOSFET of  claim 4 , wherein said SOI substrate has a substantially flat top surface.  
   
   
       20 . The thin channel MOSFET of  claim 4 , wherein said functioning gate comprises a material selected from polysilicon, a conductive elemental metal, alloys that include at least one of said conductive elemental metals, suicides that include at least one of said conductive elemental metals, nitrides that include at least one of said conductive elemental metals, and combinations thereof.