Enhancement of p-type metal-oxide-semiconductor field effect transistors

Abstract

A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.

1 - 28 . (canceled)  
   
   
       29 . A structure comprising: 
 a p-type metal-oxide-semiconductor (PMOS) transistor including:    (i) a gate dielectric layer disposed over a substrate; and    (ii) a gate disposed over a portion of the dielectric layer, defining a channel therebelow,    wherein the channel is strained and comprises silicon, the strained channel is disposed proximate compressively strained Si 1-y Ge y , and the PMOS transistor has a p-type carrier mobility enhancement with respect to a PMOS transistor formed in bulk unstrained silicon.    
   
   
       30 . The structure of  claim 29 , wherein the strained channel is disposed above a relaxed material.  
   
   
       31 . The structure of  claim 29 , wherein a difference between a Ge concentration y and a Ge concentration of the substrate is approximately 0.2.  
   
   
       32 . The structure of  claim 29 , further comprising: 
 an n-type metal-oxide-semiconductor (NMOS) transistor disposed on the substrate, the NMOS transistor including a strained silicon channel.    
   
   
       33 . The structure of  claim 32 , wherein the NMOS strained silicon channel is tensilely strained.  
   
   
       34 . The structure of  claim 32 , wherein the NMOS strained silicon channel is strained by a material comprising silicon.  
   
   
       35 . The structure of  claim 29 , wherein the PMOS transistor further comprises a source and a drain disposed proximate the channel, each of the source and the drain comprising compressively strained Si 1-y Ge y .  
   
   
       36 . The structure of  claim 29 , wherein the germanium content y of the Si 1-y Ge y  is selected to define p-type carrier mobility in the strained silicon channel.  
   
   
       37 . A structure comprising: 
 a p-type metal-oxide-semiconductor (PMOS) transistor including:    (i) a gate dielectric layer disposed over a substrate; and    (ii) a gate disposed over a portion of the dielectric layer, defining a channel therebelow,    wherein the channel is strained and comprises silicon, the strained channel is disposed proximate compressively strained Si 1-y Ge y , and the PMOS transistor has a first hole mobility enhancement, the first hole mobility enhancement being approximately constant as a function of increasing vertical field.    
   
   
       38 . The structure of  claim 37 , wherein the first hole mobility enhancement is greater than a second hole mobility enhancement of a second PMOS transistor formed on a second substrate, the second PMOS transistor being substantially free of compressively strained Si 1-y Ge y .  
   
   
       39 . The structure of  claim 37 , wherein the strained channel is disposed above a relaxed material.  
   
   
       40 . The structure of  claim 37 , wherein a difference between a Ge concentration y and a Ge concentration of the substrate is approximately 0.2.  
   
   
       41 . The structure of  claim 37 , further comprising: 
 an n-type metal-oxide-semiconductor (NMOS) transistor disposed on the substrate, the NMOS transistor including a strained silicon channel.    
   
   
       42 . The structure of  claim 41 , wherein the NMOS strained silicon channel is tensilely strained.  
   
   
       43 . The structure of  claim 41 , wherein the NMOS strained silicon channel is strained by a material comprising silicon.  
   
   
       44 . The structure of  claim 37 , wherein the PMOS transistor further comprises a source and a drain disposed proximate the channel, each of the source and the drain comprising compressively strained Si 1-y Ge y .