Nonvolatile memory with undercut trapping structure

Abstract

The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.

1 - 52 . (canceled)  
   
   
       53 . A nonvolatile memory with undercut trapping structure, said nonvolatile memory comprising: 
 a semiconductor substrate;    a gate oxide formed on said semiconductor substrate;    a gate structure formed on said gate oxide, wherein said gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into said gate structure;    an isolation layer formed over the sidewall of said gate structure;    a first carrier trapping structure formed on a first sidewall of said isolation layer and filled into said undercut structure to define a first digital status;    a second carrier trapping structure formed on a second sidewall of said isolation layer and filled into said undercut structure to define a second digital status; and    source and drain regions formed adjacent to said gate structure and under said undercut structure.    
   
   
       54 . The nonvolatile memory of  claim 53 , further comprising pocket ion implantation region located adjacent to said source and drain regions and under said undercut structure, wherein the conductive type of the pocket ion implantation region is opposite to the one of the source and drain regions.  
   
   
       55 . The nonvolatile memory of  claim 53 , further comprising: 
 lightly doped drain region adjacent to said source and drain regions and under said undercut structure, wherein the junction of said lightly doped drain region is shallower than the one of said source and drain regions and said lightly doped drain region is closer to the channel under said gate structure than said source and drain regions.    
   
   
       56 . The nonvolatile memory of  claim 55 , further comprising pocket ion implantation region located adjacent to said lightly doped drain region and under said undercut structure, wherein the conductive type of the pocket ion implantation region is opposite to the one of the source and drain regions.  
   
   
       57 . The nonvolatile memory of  claim 53 , further comprising: 
 double doped drain region adjacent to said source and drain regions and under said undercut structure, wherein the junction of said double doped drain region is deeper than the one of said source and drain regions and said double doped drain region is closer to the channel under said gate structure than said source and drain regions.    
   
   
       58 . The nonvolatile memory of  claim 57 , further comprising pocket ion implantation region located adjacent to said double doped drain region and under said undercut structure, wherein the conductive type of the pocket ion implantation region is opposite to the one of the source and drain regions.  
   
   
       59 . The nonvolatile memory of  claim 53 , wherein the undercut-filling material filled into said undercut structure includes nitride or the material having energy gap lower than 6 eV.  
   
   
       60 . The nonvolatile memory of  claim 53 , further comprising spacers attached on said first and second carrier trapping structures, wherein said spacers are formed of oxide or the material having energy gap larger than 7 eV.  
   
   
       61 . The nonvolatile memory of  claim 53 , wherein said isolation layer is formed of oxide or the material having energy gap larger than 7 eV.  
   
   
       62 . The nonvolatile memory of  claim 53 , wherein said first carrier trapping structures is formed of nitride or the material having energy gap lower than 6 eV.  
   
   
       63 . The nonvolatile memory of  claim 53 , wherein said second carrier trapping structures is formed of nitride or the material having energy gap lower than 6 eV.  
   
   
       64 . The nonvolatile memory of  claim 53 , further comprising salicide formed on said gate structure and said source and drain.  
   
   
       65 . The nonvolatile memory of  claim 64 , wherein said salicide material includes TiSi 2 , CoSi 2  or NiSi.