Vertical nanotube semiconductor device structures and methods of forming the same

Abstract

Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

1 . A vertical semiconductor device structure, comprising: 
 a substrate defining a substantially horizontal plane;    a gate electrode projecting vertically from said substrate;    at least one semiconducting nanotube extending vertically through said gate electrode between opposite first and second ends;    a gate dielectric electrically insulating said at least one semiconducting nanotube from said gate electrode;    a source electrically coupled with said first end of said at least one semiconducting nanotube; and    a drain electrically coupled with said second end of said at least one semiconducting nanotube.    
     
     
         2 . The semiconductor device structure of  claim 1  wherein said source is composed of a catalyst material effective for growing said at least one semiconducting nanotube.  
     
     
         3 . The semiconducting device structure of  claim 1  wherein said drain is composed of a catalyst material effective for growing said at least one semiconducting nanotube.  
     
     
         4 . The semiconductor device structure of  claim 1  further comprising: 
 an insulating layer disposed between said drain and said gate electrode for electrically isolating said drain from said gate electrode.    
     
     
         5 . The semiconductor device structure of  claim 1  further comprising: 
 an insulating layer disposed between said source and said gate electrode for electrically isolating said source from said gate electrode.    
     
     
         6 . The semiconducting device structure of  claim 1  wherein said at least one semiconducting nanotube is composed of arranged carbon atoms.  
     
     
         7 . The semiconducting device structure of  claim 1  wherein said at least one semiconducting nanotube defines a channel region of a field effect transistor having a channel along which current flow is regulated by application of a control voltage to said gate electrode.  
     
     
         8 . The semiconducting device structure of  claim 1  wherein said at least one semiconducting nanotube is oriented substantially perpendicular to said horizontal plane.  
     
     
         9 . The semiconducting device structure of  claim 1  further comprising: 
 a plurality of semiconducting nanotubes extending vertically through said gate electrode.    
     
     
         10 . The semiconducting device structure of  claim 1  wherein said gate dielectric is disposed on said at least one semiconducting nanotube.  
     
     
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         25 . A semiconductor device structure, comprising: 
 a substrate defining a substantially horizontal plane;    a conductive first plate disposed on said substrate,    at least one nanotube projecting vertically from said first plate and electrically coupled with said first plate;    a conductive second plate positioned vertically above said first plate; and    a dielectric layer electrically isolating said second plate from said first plate and said at least one carbon nanotube.    
     
     
         26 . The semiconductor device structure of  claim 25  wherein said at least one nanotube has a conducting molecular structure.  
     
     
         27 . The semiconductor device structure of  claim 25  wherein said at least one nanotube has a semiconducting molecular structure.  
     
     
         28 . The semiconducting device structure of  claim 25  wherein said dielectric layer defines a coating that encases said at least one nanotube.  
     
     
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