Semiconductor device having porous structure

Abstract

A semiconductor device having a hollow structure includes: a substrate on which a wiring layer is formed; a low-dielectric layer with a porosity of 6% to 25% having vias and trenches and having voids between adjacent vias; and a contact layer of copper with which the vias and trenches are filled. The contact layer is in contact with the wiring layer and an upper surface of the contact layer is exposed from the dielectric layer.

1 . A semiconductor device having a hollow structure comprising: 
 a substrate on which a wiring layer is formed;    a low-dielectric layer having a porosity of 6% to 25%, said low-dielectric layer having vias and trenches formed therethrough and having voids between adjacent vias; and    a contact layer of copper with which the vias and trenches are filled, wherein the contact layer is in contact with the wiring layer and an upper surface of the contact layer is exposed from the dielectric layer.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the low-dielectric layer having voids has a dielectric constant of 2.3 or less.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein the low-dielectric layer and the contact layer are laminated multiple times.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein the voids are air gaps, and the vias and the air gaps are substantially of equal height.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein the material of the low-dielectric layer has a dielectric constant of 2.9 or less.  
   
   
       6 . The semiconductor device according to  claim 1 , wherein the low-dielectric layer is comprised of a first low-dielectric layer formed on the substrate and a second low-dielectric layer formed on the first low-dielectric device.  
   
   
       7 . The semiconductor device according to  claim 6 , further comprising an etch stop layer between the first low-dielectric layer and the second low-dielectric layer.  
   
   
       8 . The semiconductor device according to  claim 1 , wherein the substrate further includes a cap layer on which the low-dielectric layer is formed.  
   
   
       9 . The semiconductor device according to  claim 6 , wherein the first low-dielectric layer has a dielectric constant of 3.0 or less.  
   
   
       10 . The semiconductor device according to  claim 9 , wherein the first low-dielectric layer has compressive stress.  
   
   
       11 . The semiconductor device according to  claim 6 , wherein the first low-dielectric layer is deposited by a combination of dimethyldimethoxysilane (DMDMOS) with divinyldimethylsilane (DVDMS) or oxygen-containg molecules.  
   
   
       12 . The semiconductor device according to  claim 6 , wherein the second low-dielectric layer has a dielectric constant of 2.6 or less.  
   
   
       13 . The semiconductor device according to  claim 12 , wherein the second low-dielectric layer has compressive stress.  
   
   
       14 . The semiconductor device according to  claim 6 , wherein the second low-dielectric layer is deposited by a combination of dimethyldimethoxysilane (DMDMOS) with divinyldimethylsilane (DVDMS) or oxygen-containg molecules.  
   
   
       15 . The semiconductor device according to  claim 1 , wherein the height of the voids is in the range of 1 nm to 100 nm.  
   
   
       16 . The semiconductor device according to  claim 1 , wherein the vias and the voids are substantially of equal height.