Method and apparatus handling locks

Abstract

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.

1 - 15 . (canceled)  
     
     
         16 . A method comprising:  
       in response to a determination that a locked μOP is an oldest μOP in a replay loop, draining stores in a buffer memory and, in parallel therewith, checking for a special event; and  
       in response to a verification that the special event is clear and a verification that the stores in the buffer memory are drained, providing a lock ready signal.  
     
     
         17 . The method of  claim 16 , further comprising accepting the locked μOP in response to receipt of the lock ready signal.  
     
     
         18 . The method of  claim 16 , further comprising executing a lock sequence in response to acceptance of the locked μOP.  
     
     
         19 . A method comprising:  
       in response to a determination that a locked μOP is an oldest μOP in a replay loop, checking for a special event; and  
       in response to a verification that the special event is clear, providing a lock ready signal.  
     
     
         20 . The method of  claim 19 , further comprising accepting the locked μOP in response to receipt of the lock ready signal.  
     
     
         21 . The method of  claim 19 , further comprising executing a lock sequence in response to acceptance of the locked μOP.  
     
     
         22 . A method comprising:  
       executing a lock protocol for a cache lock associated with a first thread of a processing device;  
       executing the lock protocol for a cache lock associated with a second thread of the processing device; and  
       performing a lock sequence for the cache lock associated with the first thread while performing a lock sequence for the cache lock associated with the second thread.  
     
     
         23 . The method of  claim 22 , wherein performing the lock sequence for the cache lock associated with each of the first and second threads comprises:  
       acquiring ownership of a memory location associated with the cache lock;  
       performing an atomic operation on data stored at the memory location; and  
       releasing ownership of the memory location.  
     
     
         24 . The method of  claim 23 , wherein performing the atomic operation comprises:  
       performing a load operation to access the data stored at the memory location;  
       performing a modify operation on the data; and  
       performing a store instruction to write modified data to the memory location.  
     
     
         25 - 42 . (canceled)