Programmable frequency multiplier

Abstract

In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

1 . An integrated circuit comprising: 
 a clock multiplier circuit coupled to receive an input signal and configured to generate an output clock signal, wherein the clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal, and wherein the number of pulses is selectable; and    a core configured to be clocked by the output clock signal.    
   
   
       2 . The integrated circuit as recited in  claim 1  wherein the edge of the input signal comprises the rising edge.  
   
   
       3 . The integrated circuit as recited in  claim 1  wherein the edge of the input signal comprises the falling edge.  
   
   
       4 - 25 . (canceled)