Mask ROM and the method of forming the same and the scheme of reading the device

Abstract

The structure of the nonvolatile memory comprises a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.

1 . A method of forming nonvolatile memory, said method comprising: 
 providing a semiconductor substrate having gate dielectric layer formed thereon, a conductive layer formed on said gate dielectric layer and a first photo-resist pattern formed on said conductive layer;    etching said gate dielectric and said conductive layer to form a gate on said semiconductor substrate using said first photo-resist pattern as an etching mask;    removing said first photo-resist pattern;    patterning a second photo-resist pattern on said semiconductor substrate to expose selected side of said semiconductor substrate;    performing a first ion implantation to implant ions into said selected side of said semiconductor substrate to form a first implanted region by using said second photo-resist pattern as a code implanting mask.    
   
   
       2 . The method of  claim 1 , further comprising forming silicide on said first implanted region.  
   
   
       3 . The method of  claim 1 , wherein said gate dielectric layer includes oxide.  
   
   
       4 . The method of  claim 3 , wherein said oxide includes silicon dioxide.  
   
   
       5 . The method of  claim 1 , wherein said gate dielectric layer is  
   
   
       6 . The method of  claim 5 , wherein said dielectric constant is around 3-100.  
   
   
       7 . The method of  claim 5 , wherein said material with high dielectric constant is selected from Ta 2 O 5 , Al 2 O 3 , ZrO 2 , HfO 2 , Gd 2 O 3  or Y 2 O 3 .  
   
   
       8 . The method of  claim 1 , wherein the ion source for said first ion implantation is selected from the group consisting of phosphorus, arsenic, boron and the combination thereof.  
   
   
       9 . The method of  claim 1 , further comprises a step of performing an optional pocket ion implantation after the formation of said gate, wherein the conductive type of said pocket ion implantation region is opposite to the one of said first implanted region.  
   
   
       10 . A method of forming nonvolatile memory, said method comprising: 
 providing a semiconductor substrate having gate dielectric layer formed thereon, a conductive layer formed on said gate dielectric layer and a first photo-resist pattern formed on said conductive layer;    etching said gate dielectric and said conductive layer to form a gate on said semiconductor substrate using said first photo-resist pattern as an etching mask;    removing said first photo-resist pattern;    patterning a second photo-resist pattern on said semiconductor substrate to expose selected side of said gate;    performing a first ion implantation to implant ions into said selected side of said gate to form a first implanted region by using said second photo-resist pattern as an implanting mask;    removing said second photo-resist pattern;    forming an isolation layer onto said gate;    forming spacers attached on sidewalls of said isolation layer;    performing a second ion implantation to implant ions into said semiconductor substrate to form second implanted regions by using said gate and said spacers as an implanting mask.    
   
   
       11 . The method of  claim 10 , wherein said gate dielectric layer includes oxide.  
   
   
       12 . The method of  claim 11 , wherein said oxide includes silicon dioxide.  
   
   
       13 . The method of  claim 10 , wherein said gate dielectric layer is formed by the material with high dielectric constant.  
   
   
       14 . The method of  claim 13 , wherein said dielectric constant is around 3-100.  
   
   
       15 . The method of  claim 13 , wherein said material with high dielectric constant is selected from Ta 2 O 5 , Al 2 O 3 , ZrO 2 , HfO 2 , Gd 2 O 3  or Y 2 O 3 .  
   
   
       16 . The method of  claim 10 , wherein said isolation layer and spacers are formed of the material selected from oxide, nitride or the combination thereof.  
   
   
       17 . The method of  claim 10 , wherein the ion source for said first and said second ion implantations is selected from the group consisting of phosphorus, arsenic, boron and the combination thereof.  
   
   
       18 . The method of  claim 10 , further comprises a step of performing an optional pocket ion implantation after the formation of said gate, wherein the conductive type of said pocket ion implantation region is opposite to the one of said first and second implanted regions.  
   
   
       19 - 34 . (canceled)