Control of dopant diffusion from buried layers in bipolar integrated circuits

Abstract

An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors ( 30, 50, 60 ), each having a buried collector region ( 26 ′). A carbon-bearing diffusion barrier ( 28 c ) is disposed over the buried collector region ( 26 ′), to inhibit the diffusion of dopant from the buried collector region ( 26 ′) into the overlying epitaxial layer ( 28 ). The diffusion barrier ( 28 c ) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer ( 28 ), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks ( 52, 62 ) may be used to define the locations of the buried collector regions ( 26 ′) that are to receive the carbon; for example, portions underlying eventual collector contacts ( 33, 44 c ) may be masked from the carbon implant so that dopant from the buried collector region ( 26 ′) can diffuse upward to meet the contact ( 33 ). MOS transistors ( 70, 80 ) including the diffusion barrier ( 28 ) are also disclosed.

1 - 13 . (canceled)  
   
   
       14 . An integrated circuit comprising at least a first bipolar transistor, comprising 
 a first buried collector region substantially free of carbon;    an epitaxially-grown silicon-containing layer, substantially free of carbon, overlying the first buried collector region;    a diffusion barrier layer comprised of a carbon-bearing substance disposed near an interface between the first buried collector region and the silicon-containing layer;    a first base layer, substantially free of carbon, at a surface of the silicon-containing layer overlying the first buried collector region; and    a first emitter, substantially free of carbon, at a surface of the first base layer overlying the first buried collector region.    
   
   
       15 . The integrated circuit of  claim 14 , further comprising: 
 a collector contact extending from a surface of the integrated circuit toward the first buried collector region;    wherein the diffusion barrier is located at selected locations of the interface between the first buried collector region and the silicon-containing layer, the selected locations including locations underlying the first emitter and not including locations between the first buried collector region and the collector contact.    
   
   
       16 . The integrated circuit of  claim 14 , wherein the first buried collector region and the first emitter are of a first conductivity type; 
 and wherein the first base layer is of a second conductivity type;    and further comprising a second bipolar transistor, the second bipolar transistor comprising:    a second buried collector region of the second conductivity type, underlying the epitaxially-grown silicon-containing layer;    a diffusion barrier comprised of a carbon-bearing substance disposed near an interface between the second buried collector region and the silicon-containing layer;    a second base layer, of the first conductivity type, at a surface of the silicon-containing layer overlying the second buried collector region; and    a second emitter, of the second conductivity type, disposed at a surface of the second base layer overlying the second buried collector region.    
   
   
       17 . The integrated circuit of  claim 16 , wherein the first buried collector region comprises a region of the semiconductor layer that is doped with boron; 
 and wherein the second buried collector region comprises a region of the semiconductor layer that is doped with arsenic.    
   
   
       18 . The integrated circuit of  claim 14 , wherein the first buried collector region and the first emitter are of a first conductivity type; 
 and wherein the first base layer is of a second conductivity type;    and further comprising a second bipolar transistor, the second bipolar transistor comprising:    a second buried collector region of the first conductivity type, underlying the epitaxially-grown silicon-containing layer;    a second base layer, of the second conductivity type, at a surface of the silicon-containing layer overlying the second buried collector region; and    a second emitter, of the first conductivity type, disposed at a surface of the second base layer overlying the second buried collector region;    wherein the diffusion barrier is located at selected locations of the interface between the first buried collector region and the silicon-containing layer, the selected locations including locations underlying the first emitter and not including locations between the second buried collector region and the second emitter.    
   
   
       19 . The integrated circuit of  claim 14 , further comprising: 
 a buried insulator layer disposed under the semiconductor layer.    
   
   
       20 . The integrated circuit of  claim 14 , further comprising: 
 an MOS transistor within another portion of the epitaxially-grown silicon-containing layer at a location over a second buried collector region, wherein the diffusion barrier is disposed near an interface between the second buried collector region and the silicon-containing layer, the MOS transistor comprising:    a source region, disposed at a surface of the silicon-containing layer;    a drain region, disposed at a surface of the silicon-containing layer; and    a gate electrode, insulatively disposed over the surface of the silicon-containing region at a location between the source and drain regions.    
   
   
       21 . A metal-oxide-semiconductor transistor, comprising: 
 a source region, disposed at a surface of a semiconducting portion of a substrate;    a drain region, disposed at the surface of the semiconducting portion;    a gate electrode, insulatively disposed over the surface of the semiconducting portion at a channel location between the source and drain regions.    a carbon-containing layer disposed in the semiconducting portion below the channel location; and    a heavily-doped region disposed in the semiconducting portion below the carbon-containing layer.    
   
   
       22 . The transistor of  claim 21 , further comprising: 
 a well region, disposed in the semiconducting portion below the heavily-doped region.    
   
   
       23 . The transistor of  claim 21 , wherein the source and drain regions abut the carbon-containing layer.  
   
   
       24 . The transistor of  claim 21 , wherein the heavily-doped region has a dopant concentration that increases with increasing depth from the surface of the semiconducting portion.  
   
   
       25 . The transistor of  claim 21 , further comprising: 
 a lightly-doped well region disposed in the semiconducting portion between the carbon-containing layer and the surface of the semiconducting portion.