Inventor · disambiguated record
Angelo Pinto
Also filed as: PINTO ANGELO
53 granted patents·12 pending applications·1,416 citations·filing 1995–2021
99Inventor score
Files withTEXAS INSTRUMENTS INC41ST MICROELECTRONICS SRL7PINTO ANGELO5BABCOCK JEFFREY A4QUALCOMM INC2
Top patents by PatentIndex Score
65 records- 0198US8129246B2Advanced CMOS using super steep retrograde wellsBABCOCK JEFFREY A·Filed 2011·Granted Mar 6, 2012·120 cites·1 claims
- 0298US7883977B2Advanced CMOS using super steep retrograde wellsTEXAS INSTRUMENTS INC·Filed 2009·Granted Feb 8, 2011·124 cites·4 claims
- 0398US7655523B2Advanced CMOS using super steep retrograde wellsTEXAS INSTRUMENTS INC·Filed 2007·Granted Feb 2, 2010·124 cites·10 claims
- 0498US7501324B2Advanced CMOS using super steep retrograde wellsTEXAS INSTRUMENTS INC·Filed 2006·Granted Mar 10, 2009·121 cites·9 claims
- 0598US7199430B2Advanced CMOS using super steep retrograde wellsTEXAS INSTRUMENTS INC·Filed 2006·Granted Apr 3, 2007·138 cites·3 claims
- 0698US7064399B2Advanced CMOS using super steep retrograde wellsTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 20, 2006·148 cites·5 claims
- 0796US8247300B2Control of dopant diffusion from buried layers in bipolar integrated circuitsBABCOCK JEFFREY A·Filed 2009·Granted Aug 21, 2012·97 cites·4 claims
- 0894US6407425B1Programmable neuron MOSFET on SOITEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 18, 2002·87 cites·24 claims
- 0991US6391707B1Method of manufacturing a zero mask high density metal/insulator/metal capacitorTEXAS INSTRUMENTS INC·Filed 2001·Granted May 21, 2002·62 cites·68 claims
- 1087US8138035B2Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channelsXIONG WEIZE·Filed 2011·Granted Mar 20, 2012·7 cites·14 claims
- 1186US8703568B2Advanced CMOS using super steep retrograde wellsBABCOCK JEFFREY A·Filed 2012·Granted Apr 22, 2014·4 cites·3 claims
- 1285US7422972B2On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuitsTEXAS INSTRUMENTS INC·Filed 2005·Granted Sep 9, 2008·13 cites·4 claims
- 1385US6958523B2On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuitsTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 25, 2005·38 cites·6 claims
- 1485US6646323B2Zero mask high density metal/insulator/metal capacitorTEXAS INSTRUMENTS INC·Filed 2001·Granted Nov 11, 2003·45 cites·41 claims
- 1584US6667226B2Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor deviceTEXAS INSTRUMENTS INC·Filed 2001·Granted Dec 23, 2003·48 cites·25 claims
- 1683US6770952B2Integrated process for high voltage and high performance silicon-on-insulator bipolar devicesTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 3, 2004·29 cites·8 claims
- 1782US6660616B2P-i-n transit time silicon-on-insulator deviceTEXAS INSTRUMENTS INC·Filed 2002·Granted Dec 9, 2003·32 cites·6 claims
- 1880US9053966B2Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channelsTEXAS INSTRUMENTS INC·Filed 2014·Granted Jun 9, 2015·3 cites·2 claims
- 1980US8872220B2Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channelsTEXAS INSTRUMENTS INC·Filed 2013·Granted Oct 28, 2014·3 cites·20 claims
- 2076US6838348B2Integrated process for high voltage and high performance silicon-on-insulator bipolar devicesTEXAS INSTRUMENTS INC·Filed 2004·Granted Jan 4, 2005·18 cites·11 claims
- 2176US6465830B2RF voltage controlled capacitor on thick-film SOITEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 15, 2002·20 cites·15 claims
- 2272US8558318B2Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesPINTO ANGELO·Filed 2011·Granted Oct 15, 2013·2 cites·6 claims
- 2370US7892908B2Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2008·Granted Feb 22, 2011·2 cites·14 claims
- 2470US6794237B2Lateral heterojunction bipolar transistorTEXAS INSTRUMENTS INC·Filed 2002·Granted Sep 21, 2004·13 cites·10 claims
- 2566US6362025B1Method of manufacturing a vertical-channel MOSFETST MICROELECTRONICS SRL·Filed 1999·Granted Mar 26, 2002·33 cites·10 claims
- 2665US8410519B2Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channelsXIONG WEIZE·Filed 2012·Granted Apr 2, 2013·1 cites·19 claims
- 2764US6680504B2Method for constructing a metal oxide semiconductor field effect transistorTEXAS INSTRUMENTS INC·Filed 2001·Granted Jan 20, 2004·11 cites·7 claims
- 2862US7897994B2Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrateTEXAS INSTRUMENTS INC·Filed 2007·Granted Mar 1, 2011·1 cites·14 claims
- 2962US7767510B2Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) siliconTEXAS INSTRUMENTS INC·Filed 2007·Granted Aug 3, 2010·2 cites·23 claims
- 3061US7943479B2Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flowTEXAS INSTRUMENTS INC·Filed 2008·Granted May 17, 2011·2 cites·20 claims
- 3161US6894366B2Bipolar junction transistor with a counterdoped collector regionTEXAS INSTRUMENTS INC·Filed 2001·Granted May 17, 2005·9 cites·5 claims
- 3258US6624017B1Manufacturing process of a germanium implanted HBT bipolar transistorST MICROELECTRONICS SRL·Filed 2000·Granted Sep 23, 2003·6 cites·19 claims
- 3357US7217322B2Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layerTEXAS INSTRUMENTS INC·Filed 2004·Granted May 15, 2007·5 cites·15 claims
- 3456US9123570B2Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2013·Granted Sep 1, 2015·0 cites·6 claims
- 3556US7943451B2Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2008·Granted May 17, 2011·0 cites·15 claims
- 3655US2010304547A1Reduction of sti corner defects during spe in semicondcutor device fabrication using dsb substrate and hot technologyTEXAS INSTRUMENTS INC·Filed 2009·Application pending·0 cites
- 3754US6806159B2Method for manufacturing a semiconductor device with sinker contact regionTEXAS INSTRUMENTS INC·Filed 2002·Granted Oct 19, 2004·6 cites·13 claims
- 3852US8846487B2Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technologyPINTO ANGELO·Filed 2012·Granted Sep 30, 2014·0 cites·22 claims
- 3951US6284615B1Method and apparatus for the selective doping of semiconductor material by ion implantationST MICROELECTRONICS SRL·Filed 1999·Granted Sep 4, 2001·16 cites·5 claims
- 4050US7642197B2Method to improve performance of secondary active components in an esige CMOS technologyTEXAS INSTRUMENTS INC·Filed 2007·Granted Jan 5, 2010·3 cites·20 claims
- 4150US2009057816A1Method to reduce residual sti corner defects generated during spe in the fabrication of nano-scale cmos transistors using dsb substrate and hot technologyPINTO ANGELO·Filed 2007·Application pending·0 cites
- 4249US7897447B2Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase epitaxy (SPE) in the fabrication of nano-scale CMOS transistors using direct silicon bond substrate (DSB) and hybrid orientation technology (HOT)TEXAS INSTRUMENTS INC·Filed 2009·Granted Mar 1, 2011·0 cites·4 claims
- 4349US7855111B2Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2009·Granted Dec 21, 2010·0 cites·19 claims
- 4448US7164186B2Structure of semiconductor device with sinker contact regionTEXAS INSTRUMENTS INC·Filed 2004·Granted Jan 16, 2007·3 cites·8 claims
- 4548US6905932B2Method for constructing a metal oxide semiconductor field effect transistorTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 14, 2005·3 cites·13 claims
- 4648US2011180881A1Integration scheme for reducing border region morphology in hybrid orientation technology (hot) using direct silicon bonded (dsb) substratesTEXAS INSTRUMENTS INC·Filed 2011·Application pending·0 cites
- 4746US8043947B2Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrateTEXAS INSTRUMENTS INC·Filed 2007·Granted Oct 25, 2011·0 cites·15 claims
- 4845US11929325B2Mixed pitch track patternQUALCOMM INC·Filed 2021·Granted Mar 12, 2024·0 cites·24 claims
- 4945US6774455B2Semiconductor device with a collector contact in a depressed well-regionTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 10, 2004·2 cites·9 claims
- 5043US6927428B2Lateral heterojunction bipolar transistorTEXAS INSTRUMENTS INC·Filed 2004·Granted Aug 9, 2005·1 cites·7 claims
Showing the top 50 of 65 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →