Integration scheme for reducing border region morphology in hybrid orientation technology (hot) using direct silicon bonded (dsb) substrates

Abstract

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming ( 100 )-oriented silicon regions for NMOS and ( 110 ) regions for PMOS. Boundary regions between ( 100 ) and ( 110 ) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a ( 110 ) direct silicon bonded (DSB) layer on a ( 100 ) substrate, regions in the DSB layer are amorphized and recrystallized on a ( 100 ) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the ( 110 ) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

1 . An integrated circuit (IC) comprising:
 provided a single crystal substrate, comprised of silicon with a first crystal lattice orientation;   a layer of directly bonded silicon (DSB) with a second crystal lattice orientation formed on a top surface of said single crystal substrate;   a region with said first crystal lattice orientation formed in said DSB layer and connecting with said top surface of said single crystal substrate, formed by solid phase epitaxy (SPE);   a region of field oxide formed at a lateral boundary between said region with said first crystal lattice orientation and said region with said second crystal lattice orientation;   a first well of a first electrical type formed in said region with said first crystal lattice orientation by ion implanting a first set of dopants of said first electrical type;   a second well of a second electrical type formed in said regions with said second crystal lattice orientation by ion implanting a second set of dopants of said second electrical type;   a first MOS transistor formed in said first well, further comprising:
 a first gate dielectric layer formed on a top surface of said first well; 
 a first gate formed on a top surface of said first type of gate dielectric layer; 
 a first set of LDD offset spacers formed on lateral surfaces of said first type of gate; 
 a first set of LDD regions of said second electrical type formed in said first type of well adjacent to said first type of gate by ion implanting a second set of said second type of dopants; 
 a first set of gate sidewall spacers formed on lateral surfaces of said first type of LDD offset spacers; and 
 a first set of SD regions of said second electrical type formed in said first type of well adjacent to said first type of gate sidewall spacers by ion implanting a third set of said second type of dopants; 
   a second MOS transistor formed in said second well by a process further comprising the steps of:
 a second gate dielectric layer formed on a top surface of said second well; 
 a second gate formed on a top surface of said second type of gate dielectric layer; 
 a second set of LDD offset spacers formed on lateral surfaces of said second type of gate; 
 a second set of LDD regions of said first electrical type formed in said second type of well adjacent to said second type of gate by ion implanting a second set of said first type of dopants; 
 a second set of gate sidewall spacers formed on lateral surfaces of said second type of LDD offset spacers; and 
 a second set of SD regions of said first electrical type formed in said second type of well adjacent to said second type of gate sidewall spacers by ion implanting a third set of said first type of dopants; 
   a PMD liner formed on top surfaces of said first type of transistor, said second type of transistor and said field oxide region;   a PMD layer formed on a top surface of said PMD liner; and   contacts formed in said PMD layer and said PMD liner to make electrical connections to said first type of SD regions and said second type of SD regions.   
     
     
         2 . The IC of  claim 1 , in which crystal lattice discontinuities at a lateral boundary between regions defined for said first crystal lattice orientation and regions defined for said second crystal lattice orientation are contained in a zone less then 40 nanometers wide. 
     
     
         3 . The IC of  claim 1 , in which crystal lattice discontinuities at a lateral boundary between regions defined for said first crystal lattice orientation and regions defined for said second crystal lattice orientation are contained in a zone less then 30 nanometers wide. 
     
     
         4 . The IC of  claim 3 , in which:
 said first crystal lattice orientation is a ( 100 ) orientation;   said second crystal lattice orientation is a ( 110 ) orientation;   said first electrical type is p-type;   said second electrical type is n-type;   said first MOS transistor is an n-channel MOS transistor; and   said second MOS transistor is a p-channel MOS transistor.   
     
     
         5 . The IC of  claim 4 , in which a thickness of said DSB layer is between 100 and 250 nanometers.