Method to reduce residual sti corner defects generated during spe in the fabrication of nano-scale cmos transistors using dsb substrate and hot technology

Abstract

A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

1 . A semiconductor device with reduced residual STI corner defects formed by the process of:
 forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation;   forming a pad oxide layer on the second silicon layer;   forming a nitride layer on the pad oxide layer;   forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate;   patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench;   implanting and amorphizing an NMOS region of the direct silicon bonded substrate;   removing the photoresist;   performing solid phase epitaxy;   performing a recrystallization anneal;   completing front end processing; and   performing back end processing.   
   
   
       2 . The device of  claim 1 , wherein the first silicon layer comprises a Miller index (110) silicon and the handle substrate with a Miller index of (100). 
   
   
       3 . The device of  claim 1 , wherein the first silicon layer comprises a Miller index (100) silicon and the handle substrate with a Miller index of (110);
 patterning an NMOS region of the direct silicon bonded substrate instead of the PMOS region utilizing photoresist including a portion of the isolation trench; and   implanting and amorphizing the PMOS region of the direct silicon bonded substrate.   
   
   
       4 . The device of  claim 1 , wherein the recrystallization anneal is performed at a temperature of less than 1250 degrees Celsius. 
   
   
       5 . The device of  claim 1 , wherein the nitride layer is deposited using a technique comprising deposition by evaporation, sputtering, chemical-vapor deposition. 
   
   
       6 . The device of  claim 1 , wherein front end processing comprises at least one of the following: forming an STI liner, filling the STI trench with oxide, and chemical mechanical polishing. 
   
   
       7 . The device of  claim 1 , wherein the recrystallization anneal is performed in an environment comprising: N 2 , Ar, and H 2 . 
   
   
       8 . A method of fabricating a semiconductor device with reduced residual STI corner defects comprising:
 forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation;   forming a pad oxide layer on the second silicon layer;   forming a nitride layer on the pad oxide layer;   forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate;   patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench;   implanting and amorphizing an NMOS region of the direct silicon bonded substrate;   removing the photoresist;   performing solid phase epitaxy;   performing a recrystallization anneal;   forming an STI liner;   completing front end processing; and   performing back end processing.   
   
   
       9 . The method of  claim 8 , wherein the first silicon layer comprises a Miller index (110) silicon and the handle substrate with a Miller index of (100). 
   
   
       10 . The method of  claim 8 , wherein the first silicon layer comprises a Miller index (100) silicon and the handle substrate with a Miller index of (110). 
   
   
       11 . The method of  claim 8 , wherein the recrystallization anneal is performed at a temperature of less than 1250 degrees Celsius. 
   
   
       12 . The device of  claim 8 , wherein the recrystallization anneal is performed in an environment comprising: N 2 , Ar, and H 2 . 
   
   
       13 . The method of  claim 8 , wherein the nitride layer is deposited using a technique comprising deposition by evaporation, sputtering, chemical-vapor deposition. 
   
   
       14 . The device of  claim 8 , wherein front end processing comprises at least one of the following: filling the STI trench with oxide, and chemical mechanical polishing.