Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program

Abstract

A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

1 . A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, comprising: 
 extracting at least one of two edges extended from a vertex of the design pattern;    measuring a length of the extracted edge;    determining whether or not the length of the measured edge is shorter than a predetermined value;    extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value; and    reshaping the design pattern to match positions of the two extracted vertexes with each other.    
   
   
       2 . A design pattern correcting method of correcting a design pattern according to  claim 1 , wherein a point at which edges other than the extracted edge are extended and intersected is regarded as a new vertex to match the positions of the two vertexes with each other.  
   
   
       3 . A design pattern correcting method of correcting a design pattern according to  claim 1 , wherein, when it is determined that the lengths of the two edges are shorter than the predetermined value, the design pattern is reshaped to match the positions of two vertexes other than a common vertex of the edges with each other.  
   
   
       4 . A design pattern correcting method of correcting a design pattern according to  claim 3 , wherein a point at which edges other than the extracted edge are extended and intersected is regarded as a new vertex to match the positions of the two vertexes with each other.  
   
   
       5 . A design pattern correcting method of correcting a design pattern according to  claim 1 , wherein the predetermined value is less than a minimum width which limits the design pattern.  
   
   
       6 . A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, comprising: 
 extracting an edge extended from a vertex of the design pattern;    measuring a length of the extracted edge;    determining whether or not the length of the measured edge is shorter than a predetermined value;    judging that a design rule is violated to output an error if it is determined that the length of the edge is shorter than the predetermined value; and    reshaping the design pattern not to violate the design rule.    
   
   
       7 . A design pattern correcting method of correcting a design pattern according to  claim 6 , wherein the predetermined value is less than a minimum width which limits the design pattern.  
   
   
       8 . A design pattern process proximity effect correcting method of correcting a design pattern process proximity effect of a design pattern in relation to a minute step of the design pattern, comprising: 
 extracting an edge extended from a predetermined vertex of the design pattern;    measuring a length of the extracted edge;    determining whether or not the length of the measured edge is shorter than a predetermined value;    extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value;    dividing the extracted edge into edge units for pattern correction with a vertex excluding the two extracted vertexes as a starting point;    allocating a correction value for said each divided edge unit; and    resizing the design pattern corresponding to the correction value for said each allocated edge unit.    
   
   
       9 . A design pattern process proximity effect correcting method, according to  claim 8 , wherein the predetermined value is less than a minimum width which limits the design pattern.  
   
   
       10 . A design pattern process proximity effect correcting method of making a process proximity effect correction on a design pattern corrected by the design pattern correcting method as recited in  claim 1 .  
   
   
       11 . A design pattern process proximity effect correcting method of making a process proximity effect correction on a design pattern corrected by the design pattern correcting method as recited in  claim 6 .  
   
   
       12 . A mask manufacturing method for manufacturing a mask by using a design pattern corrected by the design pattern process proximity effect correcting method as recited in  claim 8 .  
   
   
       13 . A mask manufacturing method for manufacturing a mask by using a design pattern corrected by the design pattern process proximity effect correcting method as recited in  claim 10 .  
   
   
       14 . A mask manufacturing method for manufacturing a mask by using a design pattern corrected by the design pattern process proximity effect correcting method as recited in  claim 11 .  
   
   
       15 . A semiconductor device manufacturing method of manufacturing a semiconductor device, comprising forming a pattern of a desired shape on a wafer by exposing the wafer to light by using a mask manufactured according to the mask manufacturing method as recited in  claim 12 .  
   
   
       16 . A semiconductor device manufacturing method of manufacturing a semiconductor device, comprising forming a pattern of a desired shape on a wafer by exposing the wafer to light by using a mask manufactured according to the mask manufacturing method as recited in  claim 13 .  
   
   
       17 . A semiconductor device manufacturing method of manufacturing a semiconductor device, comprising forming a pattern of a desired shape on a wafer by exposing the wafer to light by using a mask manufactured according to the mask manufacturing method as recited in  claim 14 .  
   
   
       18 . A program of causing a computer to execute a design pattern correcting method, comprising: 
 extracting at least one of two edges extended from a vertex of the design pattern;    measuring a length of the extracted edge;    determining whether or not the length of the measured edge is shorter than a predetermined value;    extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value; and    reshaping the design pattern to match positions of the two extracted vertexes with each other.    
   
   
       19 . A program of causing a computer to execute a design pattern correcting method, comprising: 
 extracting an edge extended from a vertex of the design pattern;    measuring a length of the extracted edge;    determining whether or not the length of the measured edge is shorter than a predetermined value;    judging that a design rule is violated to output an error if it is determined that the length of the edge is shorter than the predetermined value; and    reshaping the design pattern not to violate the design rule.    
   
   
       20 . A program of causing a computer to execute a design pattern process proximity effect correcting method, comprising: 
 extracting an edge extended from a predetermined vertex of the design pattern;    measuring a length of the extracted edge;    determining whether or not the length of the measured edge is shorter than a predetermined value;    extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value;    dividing the extracted edge into edge units for pattern correction with a vertex excluding the two extracted vertexes as a starting point;    allocating a correction value for said each divided edge unit; and    resizing the design pattern corresponding to the correction value for said each allocated edge unit.