US2005253798A1PendingUtilityA1

Image display system and image information transmission method

Assignee: HIYAMA IKUOPriority: Feb 7, 2001Filed: Jul 25, 2005Published: Nov 17, 2005
Est. expiryFeb 7, 2021(expired)· nominal 20-yr term from priority
H04N 19/103G09G 2340/02H04N 19/137G09G 5/36G06F 3/14H04N 19/12H04N 19/124H04N 19/59G09G 2340/0407
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Claims

Abstract

To provide a display device capable of displaying a moving picture with high definition and at high speed. An image display system includes: an image display unit; and a control unit. The control unit has: a block discrimination circuit portion; an image processing portion; a storage portion; and a synchronizing signal generation portion. The block discrimination circuit portion discriminates a moving picture or a still picture to process the image information in accordance with the discriminated result, in which the number of gradations for the image information processed when the discriminated result is the moving picture is lower than when the discriminated result is the still picture. Thereby, the high definition image display and the high speed moving picture display can be effected by reducing the information with lower degree of recognition.

Claims

exact text as granted — not AI-modified
1 . An image display system having an image display unit composed of a block having a plurality of pixels arranged like a matrix, with said plurality of pixels divided in m pixel block units (m is a natural number of 2 or greater), said m pixels being rewritten at a time during one scanning interval, and a block in which said m pixels are rewritten m or less times during m or less scanning intervals, and an image control unit for transmitting said image information to said image display unit, comprising: 
 a graphic control chip for processing said image information corresponding to each pixel block unit with the information of block state appended, and controlling a data transfer period corresponding to the state of said image information, where said plurality of pixels are divided into m pixel block units (m is a natural number of 2 or greater); and    a memory for storing the image information processed by said graphic control chip.    
   
   
       2 . An image display system having an image display unit composed of a block having a plurality of pixels arranged like a matrix, with said plurality of pixels divided into m pixel block units (m is a natural number of 2 or greater), said m pixels being rewritten at a time during one scanning interval, and a block in which said m pixels are rewritten m or less times during m or less scanning intervals, and an image control unit for transmitting said image information to said image display unit, 
 wherein said image control unit comprises:    a block state discrimination circuit for discriminating a state of said image information corresponding to one screen in a pixel block unit to append said state information to said image information corresponding to said pixel block unit;    a graphic control chip for processing said image information corresponding to each pixel block unit with the information of state appended by said block state discrimination circuit, and controlling a data transfer period corresponding to the state of said image information; and    a memory for storing the image information processed by said graphic control chip, said memory provided corresponding to said state discriminated by said block state discrimination circuit.    
   
   
       3 . An image display system, comprising: 
 an image generation unit for generating the image information;    an image display unit composed of a block having a plurality of pixels arranged like a matrix, with said plurality of pixels divided into m pixel block units (m is a natural number of 2 or greater), said m pixels being rewritten at a time during one scanning interval, and a block in which said m pixels are rewritten m or less times during m or less scanning intervals; and    an image control unit for transmitting said image information to said image display unit,    wherein; said image information generation unit comprises a receiver for receiving an image signal and a CPU for controlling said image signal received by said receiver; and    said image control unit comprises a graphic control chip for processing said image information corresponding to each pixel block unit with the information of block state appended, and controlling a data transfer period corresponding to the state of said image information, where said plurality of pixels are divided into m pixel block units (m is a natural number of 2 or greater), and a memory for storing the image information processed by said graphic control chip.    
   
   
       4 . An image display system, comprising: 
 an image generation unit for generating the image information;    an image display unit composed of a block having a plurality of pixels arranged like a matrix, with said plurality of pixels divided into m pixel block units (m is a natural number of 2 or greater), said m pixels being rewritten at a time during one scanning interval, and a block in which said m pixels are rewritten m or less times during m or less scanning intervals; and    an image control unit for transmitting said image information to said image display unit,    wherein; said image information generation unit comprises a receiver for receiving an image signal and a CPU for controlling said image signal received by said receiver; and    said image control unit comprises a block state discrimination circuit for discriminating a state of said image information corresponding to one screen in a pixel block unit to append the information of said state to said image information corresponding to said pixel block unit, a graphic control chip for processing said image information corresponding to each pixel block unit with the information of state appended by said block state discrimination circuit, and controlling a data transfer period corresponding to the state of said image information, and a memory for storing the image information processed by said graphic control chip, said memory provided corresponding to said state discriminated by said block state discrimination circuit.

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