Defect identification system and method for repairing killer defects in semiconductor devices

Abstract

A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

1 . A method of repairing killer defects in a semiconductor die prior to completion of semiconductor processing comprising: 
 identifying a die having a killer defect;    determining a location and action for a minimally invasive repair;    implementing the repair action at the repair location; and    continuing processing of the semiconductor die.    
   
   
       2 . The method of  claim 1  wherein the step of determining includes: 
 defining a grid structure overlaying an area of the die containing the defect;    analyzing the grid structure to locate squares in the grid structure containing portions of the defect; and    determining a minimum number of squares to modify in order to correct the defect.    
   
   
       3 . The method of  claim 1  wherein the killer defect comprises a shorting connection between conductors and the step of repairing comprises cutting the shorting connection.  
   
   
       4 . The method of  claim 1  wherein the killer defect comprises an open conductor space and the step of repairing comprises deposition of conductor material in the open conductor space.  
   
   
       5 . The method of  claim 3  wherein the step of cutting comprises one of focused ion beam etching, laser etching and microchemical machining.  
   
   
       6 . The method of  claim 4  wherein the step of deposition comprises laser assisted chemical deposition.  
   
   
       7 . The method of  claim 2  wherein the step of determining a minimum number of squares comprises: 
 defining the grid structure by columns and rows;    computing the number of squares in each column that would require clearing to remove the defect;    identifying a column having a minimum number of squares requiring clearing;    repeating the steps of computing and identifying squares for each row to locate a row having a minimum number of squares requiring clearing;    comparing the minimum number of squares in the column to the minimum number of squares in the row to effect clearing; and    selecting the one of the column and the row having a minimum number of squares requiring clearing.    
   
   
       8 . The method of  claim 7  and including the further steps of determining a minimum width for clearing the defect and clearing other squares to achieve the minimum width.  
   
   
       9 . A method for improving semiconductor yield by in-line repair of defects during manufacturing comprising: 
 inspecting dies on a wafer after a selected layer is formed on the dies;    identifying defects in each of the dies;    classifying the identified defects as killer or non-critical;    for each killer defect determining an action to correct the defect;    repairing the defect; and    returning the wafer to a next process step.    
   
   
       10 . The method of  claim 9  wherein the killer defect comprises a shorting connection between conductors and the step of repair comprises cutting the connection.  
   
   
       11 . The method of  claim 10  wherein the step of cutting comprises one of focused ion beam etching, laser etching and microchemical machining.  
   
   
       12 . The method of  claim 9  wherein the defect comprises an open space in a conductor and the step of repair comprises laser assisted microchemical deposition.