Method and apparatus for delaying interfering accesses from other threads during transactional program execution

Abstract

One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

1 - 25 . (canceled)  
     
     
         26 . An apparatus that facilitates delaying memory accesses directed to cache lines associated with transactional execution, comprising: 
 a transactional execution mechanism configured to commence transactional execution of a block of instructions within a thread executing on a processor; and    a request processing mechanism configured to receive a request from a requesting thread to perform a memory access involving a cache line;    wherein if performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the request processing mechanism is configured to perform the memory access at a later time when the memory access will not interfere with the transaction.    
     
     
         27 . The apparatus of  claim 26 , wherein while performing the memory access at a later time when the memory access will not interfere with the transaction, the request processing mechanism is configured to: 
 store copy-back information for the cache line to enable the cache line to be copied back to the requesting thread, and to    perform the memory access and copy the cache line back to the requesting thread at a later time when the memory access will not interfere with the transactional execution.    
     
     
         28 . The apparatus of  claim 26 , wherein performing the memory access involves copying the cache line back to the requesting thread.  
     
     
         29 . The apparatus of  claim 26 , wherein it is possible to delay an interfering memory access if a commit operation is in the process of committing updates made during the transactional execution to the architectural state of the processor, and if the memory access is directed to a cache line for which a last update made during the transactional execution has not yet been committed to the architectural state of the processor.  
     
     
         30 . The apparatus of  claim 29 , wherein the request processing mechanism is configured to copy back a cache line associated with a delayed memory access to the requesting thread after the last update to the cache line during the transactional execution is committed to the architectural state of the processor.  
     
     
         31 . The apparatus of  claim 29 , wherein the request processing mechanism is configured to copy back a cache line associated with a delayed memory access to the requesting thread after all updates that took place during the transactional execution are committed to the architectural state of the processor.  
     
     
         32 . The apparatus of  claim 29 , wherein it is possible to delay an interfering memory access prior to the commit operation; and 
 wherein if the transactional execution fails prior to the commit operation, the request processing mechanism is configured to copy back cache lines for any interfering memory accesses that have been delayed during the transactional execution, wherein the data that is copied back is original cache line data, which has not been modified during the transactional execution.    
     
     
         33 . The apparatus of  claim 26 , wherein if the memory access will interfere with the transactional execution and if it is not possible to delay the memory access, the transactional execution mechanism is configured to: 
 discard changes made during the transactional execution;    allow the memory access to complete; and to    attempt to re-execute the block of instructions.    
     
     
         34 . The apparatus of  claim 33 , wherein while discarding changes made during the transactional execution, the transactional execution mechanism is configured to: 
 discard register file changes made during the transactional execution;    clear load marks from cache lines;    drain store buffer entries generated during the transactional execution; and to    clear store marks from cache lines.    
     
     
         35 . The apparatus of  claim 26 , wherein an interfering memory access can include: 
 a store by another thread to a cache line that has been load-marked by the thread; and    a load or a store by another thread to a cache line that has been store-marked by the thread.    
     
     
         36 . The apparatus of  claim 26 , wherein while commencing transactional execution, the transactional execution mechanism is configured to: 
 save processor registers;    configure the processor to load-mark cache lines during loads that take place during transactional execution;    configure the processor to store-mark cache lines during stores that take place during transactional execution; and to    configure the processor to continually monitor data references from other threads to detect interfering data references.    
     
     
         37 . The apparatus of  claim 26 , wherein if transactional execution completes without encountering an interfering memory access from another thread, the transactional processing mechanism is configured to: 
 commit changes made during the transactional execution to the architectural state of the processor; and to    resume normal non-transactional execution of the program past the block of instructions.    
     
     
         38 . The apparatus of  claim 37 , wherein while committing changes made during transactional execution, the transactional processing mechanism is configured to: 
 clear load marks from cache lines;    commit store buffer entries generated during the transactional execution to memory, wherein if a store buffer entry contains a last update made to a cache line during the transactional execution, committing the store buffer entry involves unmarking the corresponding cache line; and to    commit register file changes made during transactional execution.    
     
     
         39 . The apparatus of  claim 26 , wherein the request to perform the memory access can include: 
 a request-to-own (RTO) signal; or    a request-to-share (RTS) signal.    
     
     
         40 . A method for delaying memory accesses directed to cache lines associated with transactional execution, comprising: 
 commencing transactional execution of a block of instructions within a thread executing on a processor; and    receiving a request from a requesting thread to perform a memory access involving a cache line;    wherein if performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the method further comprises, performing the memory access at a later time when the memory access will not interfere with the transaction.    
     
     
         41 . The method of  claim 40 , wherein performing the memory access at a later time when the memory access will not interfere with the transaction involves: 
 storing copy-back information for the cache line to enable the cache line to be copied back to the requesting thread, and    performing the memory access and copying the cache line back to the requesting thread at a later time when the memory access will not interfere with the transactional execution.    
     
     
         42 . The method of  claim 40 , wherein performing the memory access involves copying the cache line back to the requesting thread.  
     
     
         43 . The method of  claim 40 , wherein it is possible to delay an interfering memory access if a commit operation is in the process of committing updates made during the transactional execution to the architectural state of the processor, and if the memory access is directed to a cache line for which a last update made during the transactional execution has not yet been committed to the architectural state of the processor.  
     
     
         44 . The method of  claim 43 , wherein a cache line associated with a delayed memory access is copied back to the requesting thread after the last update to the cache line during the transactional execution is committed to the architectural state of the processor.  
     
     
         45 . The method of  claim 43 , wherein a cache line associated with a delayed memory access is copied back to the requesting thread after all updates that took place during the transactional execution are committed to the architectural state of the processor.  
     
     
         46 . The method of  claim 43 , wherein it is possible to delay an interfering memory access prior to the commit operation; and 
 wherein if the transactional execution fails prior to the commit operation, the method further involves copying back cache lines for any interfering memory accesses that have been delayed during the transactional execution, wherein the data that is copied back is original cache line data, which has not been modified during the transactional execution.    
     
     
         47 . An computer system that facilitates delaying memory accesses directed to cache lines associated with transactional execution, comprising: 
 a processor;    a memory;    a transactional execution mechanism within the processor configured to commence transactional execution of a block of instructions within a thread executing on a processor; and    a request processing mechanism within the processor configured to receive a request from a requesting thread to perform a memory access involving a cache line;    wherein if performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the request processing mechanism is configured to perform the memory access at a later time when the memory access will not interfere with the transaction.