Tool for generating a re-generative functional test

Abstract

A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).

1 . A system, comprising: 
 user directives provided to indicate user desired actions;    instruction information provided to define a suite of instructions; and    a software built-in self-test engine generation tool arranged to generate a software built-in self-test engine based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device under test and activation of a re-generative functional test on the complex device under test;    wherein the software built-in self-test engine generation tool includes a test execution directive composer adapted to provide a run time environment.    
   
   
       2 . The system of  claim 1 , wherein the test execution directive composer is adapted to receive the user directives and the device constraints and create the run time environment to enable the re-generative functional test to repeatedly generate functional tests and execute generated tests on-board the complex device under test.  
   
   
       3 . The system of  claim 1 , wherein the software built-in self-test engine is to be merged with an expected test result and then loaded on-board a complex device under test so as to activate a re-generative functional test on the complex device under test and make a comparison between test results of the re-generative functional test and the expected test result to check for design validations and/or manufacturing defects.  
   
   
       4 . The system of  claim 3 , wherein the expected test result is obtained from computer modeling of the complex device under test or from a known good device.  
   
   
       5 . The system of  claim 2 , wherein the software built-in self-test engine generation tool further includes a random instruction test generator (RIT-G) composer to receive the user directives and the instruction information and generate a compact RIT-G code.  
   
   
       6 . The system of  claim 5 , wherein the software built-in self-test engine generation tool further includes a test result compaction module composer to generate a test result compaction module code.  
   
   
       7 . The system of  claim 6 , wherein the software built-in self-test engine generation tool further includes a code merger to merge code from the RIT-G composer, the test execution directive composer and the test result compaction module composer to generate the software built-in self-test engine.  
   
   
       8 . The system of  claim 7 , wherein the software built-in self-test engine generation tool is a software tool installed to generate the software built-in self-test engine, and wherein individual components of the software built-in self-test engine generation tool, including the random instruction test generator (RIT-G) composer, the test execution directive composer, the test result compaction module composer, and the code merger, are software modules written in any computer language.  
   
   
       9 . The system of  claim 8 , wherein the software built-in self-test engine generation tool is provided on a computer readable medium.  
   
   
       10 . The system of  claim 7 , wherein the software built-in self-test engine generation tool is a hardware implementation installed to generate the software built-in self-test engine.  
   
   
       11 . The system of  claim 7 , wherein the run time environment includes a test execution environment including an exception handler to handle illegal conditions such as undesirable memory accesses, deadlock, shut-down, and infinite loops, and a RIT environment to provide equivalent operating system (OS) functions needed by the RIT generator to generate the re-generative functional test.  
   
   
       12 . The system of  claim 7 , wherein the compact RIT-G code produced is a C-language program compiled by a C-compiler to produce an assembly language version of the RIT-G code, and when the run time environment, the test result compaction module code and the assembly language version of the RIT-G code are assembled by an assembler, a single program indicating the software built-in self-test engine in the target device under test's object code is obtained.  
   
   
       13 . The system of  claim 12 , wherein the compact RIT-G code includes an instruction generation module to generate individual instructions during testing application.  
   
   
       14 . The system of  claim 1 , wherein the software built-in self-test engine comprises: 
 a RIT generator including RIT machine code reside on-board the complex device under test for generating the re-generated functional test;    a test program execution module including test execution directives for providing a run time environment to store and run the re-generated functional test; and    a test result compaction module including compression machine code to compress test results of the re-generated functional test for storage on-board the complex device under test.    
   
   
       15 . The system of  claim 14 , wherein the test execution environment employs an exception handler to handle illegal conditions, including undesirable memory accesses, deadlock, shut-down, and infinite loops.  
   
   
       16 . The system of  claim 1 , wherein the complex device under test includes a microprocessor.  
   
   
       17 . The system of  claim 16 , wherein, when test patterns of the software built-in self-test engine are applied to the microprocessor from an on-board memory, the microprocessor performs the following: 
 beginning a set-up for executing test patterns;    executing the test patterns to generate a series of test sequences and associated data for respective test sequences;    running the test sequences, and at the end of the test sequences, obtaining the test results for storage in the on-board memory; and    dumping the test results of the test patterns for making a comparison with the expected test result to check for design validations and/or manufacturing defects.    
   
   
       18 . A method for generating a software built-in self-test engine comprising: 
 obtaining user directives which indicate user desired actions;    obtaining instruction information which defines a suite of instructions; and    generating a software built-in self-test engine based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device under test and activation of a re-generative functional test on the complex device under test;    wherein the software built-in self-test engine is generating by creating a run time environment to enable the re-generative functional test to repeatedly generate functional tests and execute generated tests on-board the complex device under test based on the device constraints.    
   
   
       19 . The method of  claim 18 , wherein the software built-in self-test engine is further generated by: 
 generating a compact random instruction test generator code based on the user directives and the instruction information;    generating a test result compaction module code based on the user directives and the device constraints; and    merging the compact random instruction test generator code, the run time environment and the test result compaction module code to obtain the software built-in self-test engine.    
   
   
       20 . The method of  claim 18 , wherein the software built-in self-test engine is to be merged with an expected test result and then loaded on-board a complex device under test so as to activate a re-generative functional test on the complex device under test and make a comparison between test results of the re-generative functional test and the expected test result to check for design validations and/or manufacturing defects.  
   
   
       21 . The method of  claim 20 , wherein the expected test result is obtained from computer modeling of the complex device under test or from a known good device.  
   
   
       22 . The method of  claim 19 , wherein the run time environment includes a test execution environment including an exception handler to handle illegal conditions such as undesirable memory accesses, deadlock, shut-down, and infinite loops, and a RIT environment to provide equivalent operating system functions needed by the RIT generator to generate the re-generative functional test.  
   
   
       23 . The method of  claim 19 , wherein the compact RIT-G code produced is a C-language program compiled by a C-compiler to produce an assembly language version of the RIT-G code, and when the run time environment, the test result compaction module code and the assembly language version of the RIT-G code are assembled by an assembler, a single program indicating the software built-in self-test engine in the target device under test's object code is obtained.  
   
   
       24 . The method of  claim 19 , wherein the complex device under test includes a microprocessor.  
   
   
       25 . The method of  claim 19 , wherein, when test patterns of the software built-in self-test engine are applied to the microprocessor from an on-board memory, the microprocessor performs the following: 
 beginning a set-up for executing test patterns;    executing the test patterns to generate a series of test sequences and associated data for respective test sequences;    running the test sequences, and at the end of the test sequences, obtaining the test results for storage in the on-board memory; and    dumping the test results of the test patterns for making a comparison with the expected test result to check for design validations and/or manufacturing defects.    
   
   
       26 . The method of  claim 25 , wherein the software built-in self-test engine is programmed to generate and execute one or more (“N”) instruction sequences, each sequence being executed on one or more (M) data sets during testing, where N and M represent an integer no less than “1” and are user-specified numbers used in generating the software built-in self-test engine.  
   
   
       27 . The method of  claim 26 , wherein the software built-in self-test engine is further programmed to generate one or more signatures to provide a unique identification of the test result of each test sequence and indicate whether the test result of a particular test sequence is “good” or “bad”.  
   
   
       28 . A computer readable medium having stored thereon a software built-in self-test engine generation software tool which, when executed by a host system, causes the system to perform: 
 obtaining user directives which indicate user desired actions;    obtaining instruction information which defines a suite of instructions; and    generating a software built-in self-test engine based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device under test and activation of a re-generative functional test on the complex device under test;    wherein the software built-in self-test engine is generated by creating a run time environment to enable the re-generative functional test to repeatedly generate functional tests and execute generated tests on-board the complex device under test based on the device constraints.    
   
   
       29 . The computer readable medium of  claim 28 , wherein the software built-in self-test engine comprises: 
 a random instruction test generator including compact random instruction test machine code reside on-board the complex device under test for generating the re-generated functional test;    a test program execution module including test execution directives for providing a run time environment to store and run the re-generated functional test; and    a test result compaction module including compression machine code to compress test results of the re-generated functional test for storage on-board the complex device under test.