Random access memory

Abstract

A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

1 - 22 . (canceled)  
   
   
       23 . A semiconductor memory device, comprising: 
 a substrate;    a contact region in the substrate;    a first dopant implant in the contact region, the first implant defining a first implant profile; and    a second dopant implant in the contact region, the second implant defining a second implant profile narrower and deeper than the first implant profile.    
   
   
       24 . A device according to  claim 23 , wherein the first and second dopants have the same conductivity type.  
   
   
       25 . A device according to  claim 24 , further comprising a capacitor in electrical contact with the contact region.  
   
   
       26 . A device according to  claim 25 , wherein the depth of the first dopant implant is in the range of 500 angstroms to 1000 angstroms and the depth of the second dopant implant is up to 2,000 angstroms.