Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

Abstract

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    a gate insulating film and a gate electrode which are formed on the semiconductor substrate in this order; and    a source/drain material layer formed in a hole in the semiconductor substrate, the hole being located beside the gate electrode,    wherein a side surface of the hole which is closer to the gate electrode includes at least one crystal plane of the semiconductor substrate.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the side surface of the hole includes two crystal planes, and a cross-sectional shape of the side surface is concave.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein the side surface of the hole includes two crystal planes, and a cross-sectional shape of the side surface is convex.  
   
   
       4 . The semiconductor device according to  claim 3 , wherein a buried insulating layer is formed under the hole in the semiconductor substrate.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein the side surface of the hole includes a single crystal plane perpendicular to the semiconductor substrate.  
   
   
       6 . The semiconductor device according to  claim 5 , wherein the semiconductor substrate is a silicon substrate, a surface orientation of the silicon substrate is (110), and a gate width direction of the gate electrode is a [111] direction of the silicon substrate.  
   
   
       7 . The semiconductor device according to  claim 1 , wherein the semiconductor substrate is a silicon substrate, and the side surface of the hole includes a (111) plane of the silicon substrate.  
   
   
       8 . The semiconductor device according to  claim 7 , wherein a surface orientation of the silicon substrate is (001).  
   
   
       9 . The semiconductor device according to  claim 7 , wherein a surface orientation of the silicon substrate is (110), and a gate width direction of the gate electrode is a [100] direction of the silicon substrate.  
   
   
       10 . The semiconductor device according to  claim 1 , wherein a sidewall is formed on a side surface of the gate electrode, and an upper end portion of the hole goes under the sidewall and is brought closer to a channel under the gate electrode.  
   
   
       11 . The semiconductor device according to  claim 1 , wherein the entire gate electrode is made of silicide of refractory metal.  
   
   
       12 . The semiconductor device according to  claim 1 , wherein the source/drain material layer is a SiGe layer.  
   
   
       13 . The semiconductor device according to  claim 1 , wherein the source/drain material layer is a metal layer.  
   
   
       14 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming a gate insulating film on a semiconductor substrate;    forming a gate electrode on the gate insulating film;    forming a sidewall on a side surface of the gate electrode;    forming a hole in the semiconductor substrate beside the gate electrode using any one of an organic alkaline solution and a tetramethylammonium hydroxide (TMAH) solution as an etchant, after forming the sidewall; and    forming a source/drain material layer in the hole.    
   
   
       15 . The method according to  claim 14 , 
 wherein in the step of forming the hole, a thickness of the gate electrode is reduced by the etchant, and    the method further comprises, after the step of forming the hole, the steps of:    forming a refractory metal layer on the source/drain material layer and the gate electrode; and    causing a reaction between the refractory metal layer and the gate electrode by heating the refractory metal layer and siliciding the entire gate electrode.    
   
   
       16 . The method according to  claim 15 , further comprising, before the step of forming the hole, the step of introducing p-type impurities into the gate electrode.  
   
   
       17 . The method according to  claim 14 , further comprising, before the step of forming the hole, the steps of: 
 forming a first conductivity type impurity diffusion region in the silicon substrate; and    forming a second conductivity type impurity diffusion region in the silicon substrate more deeply than the first conductivity type impurity diffusion region,    wherein, in the step of forming the hole, the hole is formed more deeply than the first conductivity type impurity diffusion region.    
   
   
       18 . The method according to  claim 17 , 
 wherein, in the step of forming the first conductivity type impurity diffusion region, impurities of a first conductivity type are introduced into the silicon substrate using the gate electrode as a mask to form a source/drain extension, and the source/drain extension is used as the first conductivity type impurity diffusion region, and    in the step of forming the second conductivity type impurity diffusion region, impurities of a second conductivity type are introduced into the silicon substrate using the gate electrode and the sidewall as a mask.    
   
   
       19 . The method according to  claim 18 , 
 wherein the step of forming the sidewall includes the steps of: forming a first sidewall on a side surface of the gate electrode; and forming a second sidewall on a side surface of the first sidewall, and    the method further comprises, after the step of forming the first sidewall, the step of forming a source/drain region by introducing impurities of the first conductivity type into the silicon substrate using the first sidewall as a mask.    
   
   
       20 . The method according to  claim 17 , wherein a p-type impurity diffusion region is formed as the first conductivity type impurity diffusion region, and an n-type impurity diffusion region is formed as the second conductivity type impurity diffusion region.  
   
   
       21 . The method according to  claim 17 , wherein a p-type impurity diffusion region is formed as the first conductivity type impurity diffusion region, and a p-type impurity diffusion region having a higher impurity concentration than that in the first conductivity type impurity diffusion region is formed as the second conductivity type impurity diffusion region.  
   
   
       22 . The method according to  claim 21 , wherein any one of a source/drain extension and a source/drain region is formed as the first conductivity type impurity diffusion region.  
   
   
       23 . The method according to  claim 14 , wherein an SOI substrate is used as the semiconductor substrate.  
   
   
       24 . The method according to  claim 14 , wherein a silicon substrate is used as the semiconductor substrate.  
   
   
       25 . The method according to  claim 24 , wherein a substrate with (001) surface orientation is used as the silicon substrate.  
   
   
       26 . The method according to  claim 24 , 
 wherein a substrate with (110) surface orientation is used as the silicon substrate, and    in the step of forming the gate electrode, the gate electrode is formed with a gate width direction being set to a [111] direction.    
   
   
       27 . The method according to  claim 24 , 
 wherein a substrate with (110) surface orientation is used as the silicon substrate, and    in the step of forming the gate electrode, the gate electrode is formed with a gate width direction being set to a [100] direction.    
   
   
       28 . The method according to  claim 14 , wherein a length by which an upper end portion of the hole goes under the sidewall is controlled by adjusting a substrate temperature when the sidewall is formed.  
   
   
       29 . The method according to  claim 14 , wherein a mixed solution of an ammonium hydroxide solution and isopropyl alcohol (IPA) is used as the organic alkaline solution.  
   
   
       30 . The method according to  claim 14 , wherein a SiGe layer is epitaxially grown as the source/drain material layer.  
   
   
       31 . The method according to  claim 14 , wherein a metal layer is formed as the source/drain material layer.  
   
   
       32 . A method of evaluating a semiconductor device, comprising the steps of: 
 removing a gate electrode of a MOS transistor, which is formed over a semiconductor substrate, by selective etching using any one of an organic alkaline solution and a TMAH solution as an etchant;    exposing a channel of the MOS transistor by removing a gate insulating film of the MOS transistor by wet etching; and    investigating a carrier distribution in the exposed channel using a microscope.    
   
   
       33 . The method according to  claim 32 , 
 wherein in the step of exposing the channel, the gate insulating film is removed using an etchant containing hydrofluoric acid, and    in the step of investigating the carrier distribution, a probe microscope is used as the microscope.    
   
   
       34 . The method according to  claim 32 , further comprising the step of forming a dielectric layer on the exposed channel, 
 wherein in the step of investigating the impurity distribution, any one of a scanning capacitance microscope and a scanning spreading resistance microscope is used as the microscope, and the carrier distribution is investigated through the dielectric layer.    
   
   
       35 . The method according to  claim 34 , wherein in the step of forming the dielectric layer, an oxide layer is formed as the dielectric layer by applying ozone to a portion of the semiconductor substrate which corresponds to the channel.  
   
   
       36 . The method according to  claim 32 , wherein a silicon substrate is used as the semiconductor substrate.