US2005287764A1PendingUtilityA1

Method of fabricating shallow trench isolation by ultra-thin simox processing

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Assignee: IBMPriority: May 30, 2003Filed: Aug 19, 2005Published: Dec 29, 2005
Est. expiryMay 30, 2023(expired)· nominal 20-yr term from priority
H10W 10/181H10W 10/061H10P 90/1908H10W 10/0148H10W 10/17
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Claims

Abstract

The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.

Claims

exact text as granted — not AI-modified
1 - 16 . (canceled)  
   
   
       17 . A structure comprising: 
 a semiconductor substrate comprising a buried insulating layer located adjacent to a portion of an isolation region that has an upper surface that is substantially coplanar with an upper surface of the semiconductor substrate, said buried insulating layer and said isolation region containing no interfacial layer therebetween and no appreciable encroachment of oxide.    
   
   
       18 . The semiconductor structure of  claim 17  wherein the buried insulating layer provides lateral device isolation, while the isolation region provides vertical device isolation.  
   
   
       19 . The semiconductor structure of  claim 17  wherein the isolation region is a shallow trench isolation region having a depth, as measured from the top surface of the semiconductor substrate, of about 1 μm or less.  
   
   
       20 . The semiconductor structure of  claim 17  wherein said semiconductor substrate is a preformed silicon-on-insulator substrate.

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