Method and apparatus for interfacing between test system and embedded memory on test mode setting operation

Abstract

A method of entering memory module mounted on a memory system or a plurality of memories mounted on the memory module into a test mode, and a first register and a second register for performing the method are introduced. Each of the memory manufacturers provides a different MRS code for entering the memory into the test mode and a different method of entering the memory into the test mode from one another. As a result, the number of the test MRS is stored in the first register for controlling the memory, and the test MRS codes are programmed into the second register. Additionally, each of the bits stored in the first register used for determining the number of the test MRS corresponds to each of the second registers that store a corresponding test MRS code, respectively.

1 . A test mode interfacing method of an embedded memory, the method comprising: 
 programming test mode enter sequence data into a memory test register, the test mode enter sequence data corresponding to the embedded memory to be tested;    checking whether a test mode setting command is inputted or not during a normal operation of a system; and    accessing the test mode enter sequence data programmed in the memory test register when the test mode setting command is inputted, and then setting the embedded memory to the test mode.    
     
     
         2 . The test mode interfacing method of  claim 1 , wherein the test mode enter sequence data comprises: 
 sequence enable data for representing the number of the test mode enter sequences; and    a plurality of test mode enter command data corresponding to the number of the test mode enter sequences.    
     
     
         3 . The test mode interfacing method of  claim 2 , wherein the sequence enable data includes a set of consecutive valid bits for counting the number of the test mode enter sequences.  
     
     
         4 . The test mode interfacing method of  claim 3 , wherein each of the consecutive valid bits corresponds to each of the test mode enter command data.  
     
     
         5 . The test mode interfacing method of  claim 4 , wherein the setting the embedded memory to the test mode comprises: 
 accessing one bit among the sequence enable data;    determining whether the accessed bit has a valid bit value or an invalid bit value;    accessing the test mode enter command data corresponding to the sequence enable data in response to the valid bit;    providing a test mode setting signal to the embedded memory in response to the accessed test mode enter command data; and    repeating the accessing one bit, the determining, the accessing the test mode enter command data corresponding to the sequence enable data in response to the valid bit, and the providing a test mode setting signal as many as the number of the valid bits until the accessed sequence enable data is determined as the invalid bit value.    
     
     
         6 . The test mode interfacing method of  claim 2 , wherein the test mode enter command data includes test mode register set command data and address data.  
     
     
         7 . The test mode interfacing method of  claim 1 , wherein the memory test register includes a PCI (Peripheral Component Interconnection) configuration register of the system.  
     
     
         8 . The test mode interfacing method of  claim 1 , wherein the memory test register includes a configuration register in an AMB (Advanced Memory Buffer) of an FBDIMM (Fully Buffered Dual Inline Memory Module).  
     
     
         9 . A test mode interfacing apparatus of an embedded memory, the apparatus comprising: 
 a memory test register into which test mode enter sequence data are programmed, the test mode enter sequence data corresponding to an embedded memory to be tested; and    a controller configure to check whether a test mode setting command is inputted or not during a normal operation of a system, and configured to access the test mode enter sequence data programmed into the memory test register when the test mode setting command is inputted, and configured to set the embedded memory to the test mode.    
     
     
         10 . The test mode interfacing apparatus of  claim 9 , wherein the test mode interfacing apparatus is included in a system chip set, and wherein the memory test register includes a PCI (Peripheral Component Interconnection) configuration register in the system chip set.  
     
     
         11 . The test mode interfacing apparatus of  claim 9 , wherein the test mode interfacing apparatus is included in an AMB (Advanced Memory Buffer) chip set of an FMDIMM (Fully Buffered Dual Inline Memory Module), and wherein the memory test register includes a configuration register in the AMB chip set.  
     
     
         12 . The test mode interfacing apparatus of  claim 9 , wherein the test mode interfacing apparatus is included in an SOC (System On Chip) chip set, and wherein the memory test register includes a configuration register of the SOC chip set.  
     
     
         13 . The test mode interfacing apparatus of  claim 9 , wherein the test mode enter sequence data programmed into the memory test register comprises: 
 sequence enable data for representing the number of the test mode enter sequences; and    test mode enter command data corresponding to the number of the test mode enter sequences.    
     
     
         14 . The test mode interfacing apparatus of  claim 13 , wherein the sequence enable data includes a set of consecutive valid bits for counting the number of the test mode enter sequences.  
     
     
         15 . The test mode interfacing apparatus of  claim 14 , wherein each of the consecutive valid bits corresponds to each of the test mode enter command data.  
     
     
         16 . The test mode interfacing apparatus of  claim 15 , wherein the controller, when the test mode setting command is inputted, accesses one bit among the sequence enable data, 
 determines whether the accessed bit has a valid bit value or an invalid bit value,    accesses the test mode enter command data corresponding to the sequence enable data in response to the valid bit,    provides a test mode setting signal to the embedded memory in response to the accessed test mode enter command data, and    repeats the accessing one bit, the determining, the accessing the test mode enter command data corresponding to the sequence enable data in response to the valid bit, and the providing a test mode setting signal as many as the number of the valid bits until the accessed sequence enable data is determined as the invalid bit value.    
     
     
         17 . The test mode interfacing apparatus of  claim 13 , wherein the test mode enter command data includes test mode register set command data and address data.  
     
     
         18 . An interfacing method in which a test mode enter sequence of a memory chip is programmable, the method comprising: 
 reading one setting bit from test mode enter sequence setting register;    determining whether the read setting bit has a valid bit value or an invalid bit value;    reading corresponding enter sequence data from the test mode enter sequence data register in response to the valid setting bit;    providing a test mode setting signal to a memory chip in response to the read enter sequence data; and    performing the test mode enter sequence by repeating the reading one setting bit, the determining, the reading corresponding enter sequence data, and the providing a test mode setting signal as many as the number of the valid setting bits until the read setting bit is determined as the invalid bit value.    
     
     
         19 . The interfacing method of  claim 18 , wherein the valid setting bits include the number of test mode enter sequences of the memory chip, and are programmed into the test mode enter sequence setting register.  
     
     
         20 . The interfacing method of  claim 19 , wherein the valid setting bits are sequentially read from an LSB (Least Significant Bit) to an MSB (Most Significant Bit) of the test mode enter sequence setting register.  
     
     
         21 . The interfacing method of  claim 18 , wherein the test mode enter sequence data are sequentially pre-programmed into the test mode enter sequence data register as a data sequence corresponding to the test mode enter sequence of the memory chip.  
     
     
         22 . The interfacing method of  claim 18 , wherein the test mode enter sequence data includes the mode register set command data of the memory chip and address data.  
     
     
         23 . The interfacing method of  claim 18 , further comprising the mode register set command data of the memory chip and address data.  
     
     
         24 . An interfacing apparatus in which a test mode enter sequence of a memory chip is programmable, the apparatus comprising: 
 a test mode enter sequence setting register that stores at least one setting bit;    a test mode enter sequence data register that stores at least one enter sequence data; and    a controller configured to read one setting bit from the test mode enter sequence setting register, configured to determine whether the read setting bit has a valid bit value or an invalid bit value, configured to read corresponding enter sequence data from the test mode enter sequence data register in response to the valid setting bit, configured to provide a test mode setting signal to the memory chip in response to the read enter sequence data, and configured to perform the enter sequence by repeating the reading one setting bit, the determining, the reading corresponding enter sequence data, and the providing a test mode setting signal as many as the number of the valid setting bits until the read setting bit is determined as the invalid bit value.    
     
     
         25 . The interfacing apparatus of  claim 24 , wherein the valid setting bits includes the number of test mode enter sequences of the memory chip, and are pre-programmed in the test mode enter sequence setting register.  
     
     
         26 . The interfacing apparatus of  claim 24 , wherein the enter sequence data are sequentially pre-programmed in the test mode enter sequence data register as a data sequence corresponding to the test mode enter sequence of the memory chip.  
     
     
         27 . The interfacing apparatus of  claim 24 , wherein the interfacing apparatus corresponds to a hub mounted in a memory controller or a memory module.  
     
     
         28 . A hub for a memory module, the hub comprising: 
 a test mode enter sequence setting register that stores at least one setting bit;    a test mode enter sequence data register that stores at least one enter sequence data;    an output circuit configured to output a test mode setting signal to at least one memory chip; and    a controller configured to read one setting bit from the test mode enter sequence setting register, configured to determine whether the read setting bit has a valid bit value or an invalid bit value, configured to read corresponding enter sequence data from the test mode enter sequence data register in response to the valid setting bit, configured to provide a test mode setting signal to a memory chip in response to the read enter sequence data, and configured to perform the enter sequence by repeating the reading one setting bit, the determining, the reading corresponding enter sequence data and the providing a test mode setting signal as many as the number of the valid setting bits until the read setting bit is determined as the invalid bit value.    
     
     
         29 . A memory module comprising: 
 a plurality of memory chips that is able be set to a test mode;    a test mode enter sequence setting register that stores at least one setting bit;    a test mode enter sequence data register that stores at least one enter sequence data;    an output circuit configured to output a test mode setting signal to at least one memory chip; and    a controller configured to read one setting bit from test mode enter sequence setting register, configured to determine whether the read setting bit has a valid bit value or an invalid bit value, configured to read corresponding enter sequence data from the test mode enter sequence data register in response to the valid setting bit, configured to provide a test mode setting signal to a memory chip in response to the read enter sequence data, and configured to perform the enter sequence by repeating the reading one setting bit, the determining, the reading corresponding enter sequence data and the providing a test mode setting signal as many as the number of the valid setting bits until the read setting bit is determined as the invalid bit value.    
     
     
         30 . A system on which a memory is mounted comprising: 
 at least one memory chip that is able be set a test mode; and    a memory controller configured to read one setting bit from a first register, configured to determine whether the read setting bit has a valid bit value or an invalid bit value, configured to read corresponding enter sequence data from a second register in response to the valid setting bit, configured to provide a test mode setting signal to the memory chip in response to the read enter sequence data, and configured to perform a test mode enter sequence by repeating the reading one setting bit, the determining, the reading corresponding enter sequence data and the providing a test mode setting signal as many as the number of the valid setting bits until the read setting bit is determined as an invalid bit value.