Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry

Abstract

Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

1 - 51 . (canceled)  
   
   
       52 . Integrated circuitry comprising: 
 a semiconductive substrate having an outer surface;    a conductive line disposed over the outer surface and having a conductive portion which defines a contact pad with which electrical connection is desired;    at least one conductive plug disposed laterally proximate the contact pad and having a plug portion disposed elevationally over a portion of the contact pad; and    conductive material disposed over the contact pad and in electrical communication with at least a portion of the conductive plug.    
   
   
       53 . Integrated circuitry comprising: 
 a semiconductive substrate having an outer surface;    a conductive line disposed over the outer surface and having a first line width at one location and a second line width which is different from the first line width at another location; at least a portion of the second line width defining a contact pad with which electrical connection is desired;    a conductive plug disposed laterally proximate the contact pad and defining therewith an effective contact pad having an effective contact pad width which is greater than the second line width; and    conductive material disposed over the effective contact pad and making electrical connection with at least a portion of the conductive plug.    
   
   
       54 . Integrated circuitry comprising: 
 a semiconductive substrate having an outer surface;    a conductive line disposed over the outer surface and having a conductive line width and a target area with which electrical communication is desired;    a pair of conductive plugs disposed over the outer surface on either side of the conductive line laterally proximate the target area and self-aligned to the substrate adjacent the conductive line, the plugs and target area defining an effectively widened target area; and    conductive material disposed over and in electrical communication with at least a portion of the effectively widened target area which includes the conductive line target area.    
   
   
       55 . Integrated circuitry comprising: 
 a semiconductive substrate having an outer surface;    a first and second conductive runner comprising polysilicon disposed over the outer surface;    a contact pad comprising part of the first conductive runner; and    a conductive plug comprising polysilicon disposed over the outer surface laterally proximate and between the contact pad and the second conductive runner, the conductive plug being essentially self-aligned at and to the semiconductive substrate at two locations, one of the two locations being defined by the second conductive runner.    
   
   
       56 . The integrated circuitry of  claim 55 , wherein: 
 the first conductive runner comprises an outermost surface which defines a conductive runner height; and    the conductive plug extends away from the substrate outer surface a distance which is greater than the first conductive runner height.    
   
   
       57 . The integrated circuitry of  claim 56 , wherein the conductive plug comprises a portion which overlaps with the conductive runner's outermost surface.  
   
   
       58 . The integrated circuitry of  claim 56 , further comprising: 
 a third conductive runner disposed over the outer surface adjacent the first conductive runner; and    a second conductive plug disposed over the outer surface laterally proximate and between the contact pad and the third conductive runner, the conductive plug being essentially self-aligned at and to the semiconductive substrate at two locations, one of the two locations being defined by the third conductive runner.    
   
   
       59 . The integrated circuitry of  claim 58 , wherein the second conductive plug extends away from the substrate outer surface a distance which is greater than the first conductive runner height.  
   
   
       60 . The integrated circuitry of  claim 58 , wherein the second conductive plug comprises a portion which overlaps with the conductive runner's outermost surface.