Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby

Abstract

Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.

1 . A semiconductor chip, comprising: 
 a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof and at least a first contact pad on a portion of the upper face extending adjacent the outer edge;    an electrically insulating region on the outer edge of said semiconductor substrate, said electrically insulating region having through-hole therein; and    a connection electrode that extends through said through-hole and is electrically connected to the first contact pad.    
   
   
       2 . The semiconductor chip of  claim 1 , wherein said electrically insulating layer has a lower surface that is coplanar with the lower face of said semiconductor substrate.  
   
   
       3 . The semiconductor chip of  claim 1 , wherein a length of the through-hole is greater than a thickness of said semiconductor substrate.  
   
   
       4 . The semiconductor chip of  claim 3 , wherein a longitudinal axis of the through-hole is substantially parallel to the outer edge of said semiconductor substrate.  
   
   
       5 . The semiconductor chip of  claim 1 , further comprising a passivation layer extending on the upper face and having an opening therein that exposes the first contact pad; and wherein said electrically insulating region wraps around the outer edge and extends onto the passivation layer.  
   
   
       6 . The semiconductor chip of  claim 5 , wherein said electrically insulating region extends between the upper face and said connection electrode.  
   
   
       7 . The semiconductor chip of  claim 1 , wherein an outer edge of said electrically insulating region represents an outer edge of the semiconductor chip.  
   
   
       8 . A semiconductor chip, comprising: 
 a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof;    an electrically insulating region on the outer edge of said semiconductor substrate, said electrically insulating region having through-hole therein with a length greater than a thickness of said semiconductor substrate;    a connection electrode extending through the through-hole; and    a solder bump electrically connected to a portion of said connection electrode extending adjacent a bottom of the through-hole.    
   
   
       9 . The semiconductor chip of  claim 8 , wherein an outer edge of said electrically insulating region represents an outer edge of the semiconductor chip.  
   
   
       10 . A method of fabricating a plurality of integrated circuit chips, comprising the steps of: 
 forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon;    filling the crisscrossing grooves with an electrically insulating layer;    patterning the electrically insulating layer to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves;    filling the first and second through-holes with first and second through-chip connection electrodes, respectively; and    dicing the semiconductor wafer into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a crisscrossing pattern that overlaps with the locations of the criss-crossing grooves.    
   
   
       11 . The method of  claim 10 , wherein said dicing step is preceded by the step of removing an underside of said semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer.  
   
   
       12 . The method of  claim 11 , wherein said step of filling the first and second through-holes comprises the steps of: 
 depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes;    electroplating the first and second through-chip connection electrodes into the first and second through-holes; and    etching back the base metal layer using the first and second through-chip connection electrodes as an etching mask.    
   
   
       13 . The method of  claim 10 , wherein said step of filling the first and second through-holes comprises the steps of: 
 depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes;    electroplating the first and second through-chip connection electrodes into the first and second through-holes; and    etching back the base metal layer using the first and second through-chip connection electrodes as an etching mask.    
   
   
       14 . The method of  claim 13 , wherein said electroplating step comprises electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode.  
   
   
       15 . The method of  claim 14 , wherein said electroplating step is preceded by the step of patterning an electroplating mask on the base metal layer.  
   
   
       16 . A method of fabricating an integrated circuit chip, comprising the steps of: 
 forming a groove in a semiconductor substrate;    filling the groove with an electrically insulating region;    forming first and second through-holes in the electrically insulating region;    filling the first and second through-holes with first and second connection electrodes, respectively;    removing an underside of the semiconductor substrate to thereby expose the electrically insulating region and the first and second connection electrodes; and    dicing the semiconductor substrate into first and second semiconductor chips by cutting through the electrically insulating region at a location extending between the first and second connection electrodes.    
   
   
       17 . The method of  claim 16 , wherein said step of filling the first and second through-holes comprises electroplating first and second connection electrodes into the first and second through-holes.  
   
   
       18 . A method of processing a semiconductor wafer, comprising the steps of: 
 forming a plurality of criss-crossing grooves in a semiconductor wafer;    filling the criss-crossing grooves with an electrically insulating layer;    removing an underside of the semiconductor wafer to thereby expose a surface of the electrically insulating layer having a criss-crossing pattern; and    dicing the semiconductor wafer into a plurality of integrated circuit chips having electrically insulating edges by cutting through the electrically insulating region at locations defined by the criss-crossing pattern.    
   
   
       19 . The method of  claim 18 , wherein said removing step is preceded by the steps of: 
 forming a plurality of through-holes in the electrically insulating layer; and    filling the plurality of through-holes with a corresponding plurality of connection electrodes.    
   
   
       20 . The method of  claim 19 , wherein said removing step comprises removing an underside of the semiconductor wafer to thereby expose a surface of the electrically insulating layer and the plurality of connection electrodes.