Method of manufacturing a plurality of electronic assemblies

Abstract

A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. Each electronic assembly has a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer. The process of fabricating electronic assemblies is simplified and costs are reduced because the dies are connected to the carrier substrate at wafer level, i.e. before singulation. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.

1 . A method of manufacturing a of plurality of electronic assemblies, comprising: 
 connecting each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer to a respective one of a plurality of second conductive terminals on a carrier wafer to form a combination wafer assembly; and    singulating the combination wafer assembly between the integrated circuits to form the electronic assemblies, each electronic assembly having a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer.    
   
   
       2 . The method of  claim 1 , further comprising: 
 introducing an underfill material that is located between the device wafer and the carrier wafer before singulating the combination wafer assembly; and    curing the underfill material.    
   
   
       3 . The method of  claim 2 , wherein the underfill material is introduced into a space between the device wafer and carrier wafer after connecting the first conductive terminals to the second conductive terminals.  
   
   
       4 . The method of  claim 3 , wherein the underfill material is introduced into the space at above atmospheric pressure.  
   
   
       5 . The method of  claim 4 , further comprising: 
 placing the combination wafer assembly in a jig; and    providing the underfill material through at least a first passage in the jig.    
   
   
       6 . The method of  claim 4 , further comprising: 
 heating the underfill material before introducing the underfill material into the space.    
   
   
       7 . The method of  claim 2  wherein the underfill material is cured before singulating the combination wafer assembly.  
   
   
       8 . The method of  claim 1 , further comprising: 
 thinning the device wafer before singulating the combination wafer assembly.    
   
   
       9 . The method of  claim 8 , further comprising: 
 introducing an underfill material that is located between the device wafer and the carrier wafer before singulating the combination wafer assembly; and    curing the underfill material.    
   
   
       10 . The method of  claim 8 , wherein the carrier wafer is made of ceramic.  
   
   
       11 . The method of  claim 1 , further comprising: 
 testing a current through at least one pair, the pair including a first conductive terminal and a second conductive terminal before singulating the combination wafer assembly.    
   
   
       12 . The method of  claim 11 , wherein current is provided through a first conductor extending through the device wafer and through a second conductor extending through that carrier wafer.  
   
   
       13 . A method of manufacturing a plurality of electronic assemblies, comprising: 
 introducing an underfill material between a device wafer and a carrier wafer that form a combination wafer assembly;    curing the underfill material; and    singulating the combination wafer assembly between integrated circuits formed on the device wafer to form the electronic assemblies, each electronic assembly having a respective die from a separated portion of the device wafer and a respective carrier substrate from a separated portion of the carrier wafer, and a respective portion of the underfill material between the respective die and the respective carrier substrate.    
   
   
       14 . The method of  claim 13 , wherein the underfill material is cured before singulating the combination wafer assembly.  
   
   
       15 . The method of  claim 13 , wherein the underfill material is introduced between the device wafer and carrier wafer at above atmospheric pressure.  
   
   
       16 . A combination wafer assembly, comprising: 
 a device wafer;    a plurality of integrated circuits formed on the device wafer;    a plurality of first conductive terminals on the integrated circuits;    a carrier wafer; and    a plurality of second conductive terminals on the carrier wafer, each being connected to a respective one of the first conductive terminals.    
   
   
       17 . The combination wafer assembly of  claim 16 , wherein the integrated circuits are identical to one another.  
   
   
       18 . The combination wafer assembly of  claim 16 , further comprising: 
 a plurality of interconnection elements connecting each one of the first conductive terminals to each one of the second conductive terminals; and    an underfill material in a space between the device wafer and the carrier wafer and between the interconnection elements, the underfill material having been cured.