Semiconductor integrated circuit device and process for manufacturing the same

Abstract

In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

1 . A method for manufacturing a semiconductor integrated circuit device having a first portion for a memory array and a second portion for a circuit other than the memory array on a semiconductor substrate, which semiconductor integrated circuit device comprises: 
 a MISFET arranged in said first portion, said MISFET having first semiconductor regions and a gate electrode between said first semiconductor regions;    second semiconductor regions arranged in said second portion;    a first insulating film formed over said semiconductor substrate to cover said first and second portions;    a plurality of first openings formed simultaneously in said first insulating film above both said first and second portions;    a plurality of first conductor plugs formed in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion;    a first conductive strip formed on said first insulating film in said first portion and electrically connected to one of the first semiconductor regions of said MISFET through one of said first conductor plugs, wherein said first conductive strip is formed in a separate manufacturing step from said first conductor plugs;    a second conductive strip formed on said first insulating film in said second portion and electrically connected to said second semiconductor regions through said first conductor plugs to electrically connect said second semiconductor regions to one another through said second conductive strip, wherein said second conductive strip is formed in a separate manufacturing step from said first conductor plugs;    a second insulating film formed over said first insulating film and said first and second conductive strips;    a second opening formed in said second insulating film over an upper surface of one of the first conductor plugs formed in one of said first openings in the first insulating film and connected to the other of said first semiconductor regions of said MISFET;    a second conductor plug formed in said second opening in said second insulating film to electrically connect with said one of said first conductor plugs connected to the other of said first semiconductor regions of said MISFET; and    a third conductive strip formed on said second insulating film and electrically connected to said second conductor plug,    the method for manufacturing the semiconductor integrated circuit device comprising steps of:    forming said plurality of first openings simultaneously in said first insulating film above both said first and second portions; and    forming said plurality of first conductor plugs in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion simultaneously,    wherein one of first conductor plugs is directly physically connected to one of the first semiconductor regions and the first conductive strip in said first portion and another of the first conductor plugs is directly physically connected to one of the second semiconductor regions and the second conductive strip in the second portion.    
   
   
       2 . The method for manufacturing a semiconductor integrated circuit device according to  claim 1 , 
 wherein each of said first conductor plugs is comprised of a tungsten film.    
   
   
       3 . The method for manufacturing a semiconductor integrated circuit device according to  claim 2 , 
 wherein each of said first conductor plugs is comprised of a multilayer film of titanium nitride and tungsten.    
   
   
       4 . The method for manufacturing a semiconductor integrated circuit device according to  claim 2 , 
 wherein said second semiconductor regions comprise an n-type semiconductor region and a p-type semiconductor.    
   
   
       5 . The method for manufacturing a semiconductor integrated circuit device according to  claim 4 , 
 wherein said second conductor plug is comprised of a tungsten film.    
   
   
       6 . A method for manufacturing a semiconductor integrated circuit device having a first portion for a memory array and a second portion for a circuit other than the memory array on a semiconductor substrate, which semiconductor integrated circuit device comprises: 
 a MISFET arranged in said first portion, said MISFET having first semiconductor regions of n-type conductivity and a gate electrode between said first semiconductor regions;    a second semiconductor region of n-type conductivity and a third semiconductor region of p-type conductivity arranged in said second portion;    a first insulating film formed over said semiconductor substrate to cover said first and second portions;    a plurality of first openings formed simultaneously in said first insulating film above both said first and second portions;    a plurality of first conductor plugs each comprising a tungsten film formed in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion;    a first conductive strip formed on said first insulating film in said first portion and electrically connected to one of the first semiconductor regions of said MISFET through one of said first conductor plugs, wherein said first conductive strip is formed in a separate manufacturing step from said first conductor plugs;    a second conductive strip formed on said first insulating film in said second portion and electrically connected to said second and third semiconductor regions through said first conductor plugs to electrically connect said second and third semiconductor regions to one another through said second conductive strip, wherein said second conductive strip is formed in a separate manufacturing step from said first conductor plugs;    a second insulating film formed over said first insulating film and said first and second conductive strips;    a second opening formed in said second insulating film over an upper surface of one of the first conductor plugs formed in one of said first openings in the first insulating film and connected to the other of said first semiconductor regions of said MISFET;    a second conductor plug formed in said second opening in said second insulating film to electrically connect with said one of said first conductor plugs connected to the other of said first semiconductor regions of said MISFET; and    a third conductive strip formed on said second insulating film and electrically connected to said second conductor plug,    the method for manufacturing the semiconductor integrated circuit device comprising steps of:    forming said plurality of first openings simultaneously in said first insulating film above both said first and second portions; and    forming said plurality of first conductor plugs each comprising a tungsten film in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion simultaneously,    wherein one of first conductor plugs is directly physically connected to one of the first semiconductor regions and the first conductive strip in said first portion and another of the first conductor plugs is directly physically connected to one of the second semiconductor regions and the second conductive strip in the second portion.    
   
   
       7 . The method for manufacturing a semiconductor integrated circuit device according to  claim 6 , 
 wherein each of said first conductor plugs comprises a multi-layer film of titanium nitride and tungsten.    
   
   
       8 . The method for manufacturing a semiconductor integrated circuit device according to  claim 6 , 
 wherein said second conductor plug is comprised of a tungsten film.    
   
   
       9 . The method for manufacturing a semiconductor integrated circuit device according to  claim 1 , the semiconductor integrated circuit device further comprising: 
 first silicide layers formed between surfaces of said first semiconductor regions and said plurality of first conductor plugs formed in said openings in said first insulating film on said first semiconductor regions; and    second silicide layers formed between surfaces of said second semiconductor regions and said plurality of first conductor plugs formed in said openings in said first insulating film on said second semiconductor regions.    
   
   
       10 . The method for manufacturing a semiconductor integrated circuit device according to  claim 6 , the semiconductor integrated circuit device, further comprising: 
 first silicide layers formed between surfaces of said first semiconductor regions and said plurality of first conductor plugs formed in said openings in said first insulating film on said first semiconductor regions; and    second silicide layers formed between surfaces of said second semiconductor regions and said plurality of first conductor plugs formed in said openings in said first insulating film on said second semiconductor regions.    
   
   
       11 . A method for manufacturing a semiconductor integrated circuit device having a first portion for a memory array and a second portion for a circuit other than the memory array on a semiconductor substrate, which semiconductor integrated circuit device comprises: 
 a MISFET arranged in said first portion, said MISFET having first semiconductor regions and a gate electrode between said first semiconductor regions;    second semiconductor regions arranged in said second portion;    a first insulating film formed over said semiconductor substrate to cover said first and second portions;    a plurality of openings formed simultaneously in said first insulating film above both said first and second portions;    a plurality of conductor plugs formed in said openings in said first insulating film on one of said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion;    a first conductive strip formed on said first insulating film in said first portion and electrically connected to said one of the first semiconductor regions of said MISFET through one of said conductor plugs, wherein said first conductive strip is formed in a separate manufacturing step from said conductor plugs;    a second conductive strip formed on said first insulating film in said second portion and electrically connected to said second semiconductor regions through said conductor plugs to electrically connect said second semiconductor regions to one another through said second conductive strip, wherein said second conductive strip is formed in a separate manufacturing step from said conductor plugs; and    a second insulating film formed over said first insulating film and said first and second conductive strips,    the method for manufacturing the semiconductor integrated circuit device comprising steps of:    forming said plurality of openings simultaneously in said first insulating film above both said first and second portions; and    forming said plurality of conductor plugs in said openings in said first insulating film on said one of the first semiconductor regions in said first portion and on said second semiconductor regions in said second portion simultaneously,    wherein said one of the conductor plugs is directly physically connected to said one of the first semiconductor regions and the first conductive strip in said first portion and another of the conductor plugs is directly physically connected to one of the second semiconductor regions and the second conductive strip in the second portion.    
   
   
       12 . The method for manufacturing a semiconductor integrated circuit device according to  claim 11 , 
 wherein each of said conductor plugs is comprised of a tungsten film.    
   
   
       13 . The method for manufacturing a semiconductor integrated circuit device according to  claim 12 , 
 wherein each of said conductor plugs is comprised of a multilayer film of titanium nitride and tungsten.    
   
   
       14 . The method for manufacturing a semiconductor integrated circuit device according to  claim 12 , 
 wherein said second semiconductor regions comprise an n-type semiconductor region and a p-type semiconductor.    
   
   
       15 . A method for manufacturing a semiconductor integrated circuit device having a first portion for a memory array and a second portion for a circuit other than the memory array on a semiconductor substrate, which semiconductor integrated circuit device comprises: 
 a MISFET arranged in said first portion, said MISFET having first semiconductor regions of n-type conductivity and a gate electrode between said first semiconductor regions;    a second semiconductor region of n-type conductivity and a third semiconductor region of p-type conductivity arranged in said second portion;    a first insulating film formed over said semiconductor substrate to cover said first and second portions;    a plurality of openings formed simultaneously in said first insulating film above both said first and second portions;    a plurality of conductor plugs each comprised of a tungsten film formed in said openings in said first insulating film on one of said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion;    a first conductive strip formed on said first insulating film in said first portion and electrically connected to said one of the first semiconductor regions of said MISFET through one of said conductor plugs, wherein said first conductive strip is formed in a separate manufacturing step from said conductor plugs;    a second conductive strip formed on said first insulating film in said second portion and electrically connected to said second and third semiconductor regions through said conductor plugs to electrically connect said second and third semiconductor regions to one another through said second conductive strip, wherein said second conductive strip is formed in a separate manufacturing step from said conductor plugs; and    a second insulating film formed over said first insulating film and said first and second conductive strips,    the method for manufacturing the semiconductor integrated circuit device comprising steps of:    forming said plurality of openings simultaneously in said first insulating film above both said first and second portions; and    forming said plurality of conductor plugs each comprised of tungsten film in said openings in said first insulating film on said one of the first semiconductor regions in said first portion and on said second semiconductor regions in said second portion simultaneously,    wherein said one of the conductor plugs is directly physically connected to said one of the first semiconductor regions and the first conductive strip in said first portion and another of the conductor plugs is directly physically connected to one of the second semiconductor regions and the second conductive strip in the second portion.    
   
   
       16 . The method for manufacturing a semiconductor integrated circuit device according to  claim 15 , 
 wherein each of said conductor plugs is comprised of a multilayer film of titanium nitride and tungsten.    
   
   
       17 . The method for manufacturing a semiconductor integrated circuit device according to  claim 11 , the semiconductor integrated circuit device further comprising: 
 first silicide layers formed between surfaces of said first semiconductor regions and said plurality of conductor plugs formed in said openings in said first insulating film on said one of the first semiconductor regions; and,    second silicide layers formed between surfaces of said second semiconductor regions and said plurality of conductor plugs formed in said openings in said first insulating film on said second semiconductor regions.    
   
   
       18 . The method for manufacturing a semiconductor integrated circuit device according to  claim 15 , the semiconductor integrated circuit device further comprising: 
 first silicide layers formed between surfaces of said first semiconductor regions and said plurality of conductor plugs formed in said openings in said first insulating film on said one of the first semiconductor regions; and    second silicide layers formed between surfaces of said second semiconductor regions and said plurality of first conductor plugs formed in said openings in said first insulating film on said second semiconductor regions.    
   
   
       19 . A apparatus for manufacturing a semiconductor integrated circuit device having a first portion for a memory array and a second portion for a circuit other than the memory array on a semiconductor substrate, which semiconductor integrated circuit device comprises: 
 a MISFET arranged in said first portion, said MISFET having first semiconductor regions and a gate electrode between said first semiconductor regions;    second semiconductor regions arranged in said second portion;    a first insulating film formed over said semiconductor substrate to cover said first and second portions;    a plurality of first openings formed simultaneously in said first insulating film above both said first and second portions;    a plurality of first conductor plugs formed in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion;    a first conductive strip formed on said first insulating film in said first portion and electrically connected to one of the first semiconductor regions of said MISFET through one of said first conductor plugs, wherein said first conductive strip is formed in a separate manufacturing step from said first conductor plugs;    a second conductive strip formed on said first insulating film in said second portion and electrically connected to said second semiconductor regions through said first conductor plugs to electrically connect said second semiconductor regions to one another through said second conductive strip, wherein said second conductive strip is formed in a separate manufacturing step from said first conductor plugs;    a second insulating film formed over said first insulating film and said first and second conductive strips;    a second opening formed in said second insulating film over an upper surface of one of the first conductor plugs formed in one of said first openings in the first insulating film and connected to the other of said first semiconductor regions of said MISFET;    a second conductor plug formed in said second opening in said second insulating film to electrically connect with said one of said first conductor plugs connected to the other of said first semiconductor regions of said MISFET; and    a third conductive strip formed on said second insulating film and electrically connected to said second conductor plug,    the apparatus for manufacturing the semiconductor integrated circuit device comprising steps of:    means for forming said plurality of first openings simultaneously in said first insulating film above both said first and second portions; and    means for forming said plurality of first conductor plugs in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion simultaneously,    wherein one of first conductor plugs is directly physically connected to one of the first semiconductor regions and the first conductive strip in said first portion and another of the first conductor plugs is directly physically connected to one of the second semiconductor regions and the second conductive strip in the second portion.