US2006024943A1PendingUtilityA1
Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present
Individually held — no corporate assignee on recordPriority: Jul 30, 2004Filed: Jul 30, 2004Published: Feb 2, 2006
Est. expiryJul 30, 2024(expired)· nominal 20-yr term from priority
H10W 72/251H05K 3/346H10W 72/012
37
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P
Claims
exact text as granted — not AI-modified1 . In the fabrication of integrated circuit interconnection structures
wherein stacked layers of metal for different purposes are caused to fuse together by subjecting said layers to a fusion temperature excursion, a process for inhibiting a potential undesirable interaction of first and second adjacent layers during said fusion temperature excursion comprising the steps of:
exposing a surface of said first of said potential interacting layers,
applying a protective layer of a metal having, during said fusion temperature excursion, at least one inhibiting property for said interaction, over said exposed surface of said first of said potential interacting layers,
applying said second layer of said first and second potential interacting layers over said protective layer, and,
subjecting the assembly stack of said first, said protective and said second layers to said fusion temperature excursion.
2 . The process of claim 1 wherein said first layer is of electroless Ni(P) metallization, said protective layer is a metal taken from the group of Sn, and Cu, and said second layer is a further layer of the interconnection.
3 . The process of claim 1 wherein said first layer is of electroless Ni(P) metallization, said protective layer is a metal taken from the group of Sn, and Cu, in a thickness range of between 0.1 and 5 micron and said second layer is a further layer of the interconnection.
4 . The process of claim 1 wherein said first layer is of electroless Ni(P) metallization, said protective layer is a metal taken from the group of Sn, and Cu, in a thickness range of between 0.1 and 5 micron, said second layer is a further layer of the interconnection, and said temperature exursion is up through 250 degrees C.
5 . The process of claim 1 wherein said first layer is of electroless Ni(P) metallization, said protective layer is a metal taken from the group of Sn, and Cu, in a thickness range of between 0.1 and 5 micron, said second layer is a further layer of the interconnection, and said temperature exursion is up through 250 degrees C.
6 . The process of claim 1 wherein said first layer is of electroless Ni(P) metallization, said protective layer is a metal taken from the group of Sn, and Cu, in a thickness range of between 0.1 and 5 micron, and said second layer is a layer of Sn-rich Pb-free solders of a material taken from the group of pure Sn, Sn-3.5% Ag, Sn-0.7% Cu, Sn-3% Bi, Sn-3.5%-0.7% Cu, Sn-3.5% Ag-3% Bi, Sn-8%-Zn-3% Bi, Sn-3.5% Ag-0.7% Cu-0.5% Sb, and Sn-2.5% Ag-0.5% Cu.Join the waitlist — get patent alerts
Track US2006024943A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.