Ferroelectric memory device and method of forming the same

Abstract

A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.

1 . A ferroelectric memory device comprising: 
 an interlayer insulating layer on a semiconductor substrate;    two lower electrodes on the interlayer insulating layer;    a seed layer pattern in a space between the two lower electrodes, wherein a surface that includes the seed layer pattern and the two electrodes is planar;    a ferroelectric layer on the planar surface; and    an upper electrode on the ferroelectric layer and overlapping the two lower electrodes.    
   
   
       2 . The device as claimed in  1 , wherein the seed layer pattern is formed of a titanium oxide layer.  
   
   
       3 . The device as claimed in  1 , further comprising a hydrogen barrier pattern interposed between the lower electrode and the seed layer pattern, and between the seed layer pattern and the interlayer insulating layer.  
   
   
       4 . The device as claimed in  3 , wherein the hydrogen barrier pattern includes at least one material selected from a group consisting of aluminum oxide, silicon oxide, titanium oxide, zirconium oxide, and cesium oxide.  
   
   
       5 . The device as claimed in  1 , wherein the interlayer insulating layer includes silicon oxide and the ferroelectric layer includes at least one material selected from a group consisting of Pb(Zr,Ti)O 3 , PbTiO 3 , PbLaTiO 3 , (Ba,Sr)TiO 3 , BaTiO 3 , Ba 4 Ti 3 O 12 , SrBi 2 TaO 9 , SrTiO 3 , SrBi 2 Ta 2 O 9 , SrBi 2 (Ta,Nb) 2 O 9 , and SrBi 3 Ti 2 TaO 12 .  
   
   
       6 . The device as claimed in  1 , wherein the lower electrode and the upper electrode include at least one material selected from a group consisting of ruthenium, iridium, platinum, ruthenium oxide, iridium oxide, and platinum oxide.  
   
   
       7 . The device as claimed in  1 , further comprising a second hydrogen barrier layer on the upper electrode and on portions of the ferroelectric layer adjacent to the upper electrode.  
   
   
       8 . The device as claimed in  1 , further comprising: 
 a lower electrode contact penetrating the interlayer insulating layer to electrically connect the lower electrode with the semiconductor substrate; and    a diffusion barrier layer interposed between the lower electrode and the interlayer insulating layer, and between the lower electrode and the lower electrode contact.    
   
   
       9 . A method for forming a ferroelectric memory device, comprising: 
 forming two lower electrode patterns on an interlayer insulating layer covering a semiconductor substrate;    forming a seed layer pattern in a space between the two lower electrode patterns, wherein a surface that includes the seed layer pattern and the two lower electrode patterns is planar;    forming a ferroelectric layer on the planar surface; and    forming an upper electrode pattern on the ferroelectric layer, the upper electrode overlapping the two lower electrode patterns.    
   
   
       10 . The method as claimed in  claim 9 , wherein the ferroelectric layer covers the lower electrode patterns and the seed layer pattern.  
   
   
       11 . The method as claimed in  9 , wherein forming the seed layer pattern comprises: 
 forming a seed layer on the semiconductor substrate having the two lower electrode patterns, the seed layer filling a space between the two lower electrode patterns; and    removing a part of the seed layer by performing a planarization process, to expose the two lower electrode patterns and to leave a seed layer pattern between the two lower electrode patterns.    
   
   
       12 . The method as claimed in  11 , wherein the planarization process includes a chemical mechanical polishing process performed using a pressure for pressing a wafer in a range from about 1 to 5 psi, a pressure for fixing a wafer in a range from about 1 to 5 psig, a speed for rotating a table on which the wafer is placed in a range from about 30 to 50 rpm, and a speed for rotating a head for chucking a wafer in a range from about 10 to 30 rpm.  
   
   
       13 . The method as claimed in  11 , further comprising conformally forming a hydrogen barrier layer before forming the seed layer; and 
 removing a part of the hydrogen barrier layer by performing the planarization process, to form a hydrogen barrier pattern interposed between the lower electrode and the seed layer pattern and between the seed layer pattern and the interlayer insulating layer.    
   
   
       14 . The method as claimed in  13 , wherein the hydrogen barrier layer includes at least one material selected from a group consisting of aluminum oxide, silicon oxide, titanium oxide, zirconium oxide, and cesium oxide.  
   
   
       15 . The method as claimed in  9 , wherein the seed layer pattern includes titanium oxide.  
   
   
       16 . The method as claimed in  9 , wherein the ferroelectric layer includes at least one material selected from a group consisting of Pb(Zr,Ti)O 3 , PbTiO 3 , PbLaTiO 3 , (Ba,Sr)TiO 3 , BaTiO 3 , Ba 4 Ti 3 O 12 , SrBi 2 TaO 9 , SrTiO 3 , SrBi 2 Ta 2 O 9 , SrBi 2 (Ta,Nb) 2 O 9 , and SrBi 3 Ti 2 TaO 12 .  
   
   
       17 . The method as claimed in  9 , further comprising forming a second hydrogen barrier layer covering the upper electrode and portions of the ferroelectric layer adjacent to the upper electrode.  
   
   
       18 . A semiconductor device, comprising: 
 a first electrode;    two second electrodes;    a titanium oxide pattern, wherein the titanium oxide pattern is between the two second electrodes; and    a ferroelectric element disposed adjacent to the titanium oxide pattern and the two second electrodes, and between the first electrode and the two second electrodes,    wherein the portion of the ferroelectric element that is adjacent to the titanium oxide pattern and the two second electrodes is planar.    
   
   
       19 . The semiconductor device as claimed in  claim 18 , wherein the ferroelectric element is directly adjacent to the titanium oxide pattern and the two second electrodes.  
   
   
       20 . The semiconductor device as claimed in  claim 18 , further comprising a pair of transistors, 
 wherein the pair of transistors has a first common diffusion region and two separate second diffusion regions, and    wherein each of the second electrodes is connected to a respective one of the two separate second diffusion regions.