Interconnect line selectively isolated from an underlying contact plug

Abstract

The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed as initially partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration. In subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.

1 - 71 . (canceled)  
   
   
       72 . A processor-based system, comprising: 
 a processor; and    a memory circuit connected to said processor, wherein said memory circuit includes a memory device comprising:    a first conductive stud and a second conductive stud;    a bit line over and in electrical contact with said first conductive stud, wherein said bit line is overlying a portion of said second conductive stud; and    an insulating material separating said bit line from said portion of said second conductive stud, wherein said insulating material provides an insulating sidewall within a contact opening to said second conductive stud.    
   
   
       73 . The processor-based system of  claim 72  wherein said first conductive stud has a silicide cap and said second contact stud does not have a silicide cap.  
   
   
       74 . The processor-based system of  claim 72  wherein said sidewall extends around said contact opening to said second conductive stud and said contact opening is through an insulating layer which is over and around said bit line.  
   
   
       75 . The processor-based system of  claim 72  wherein said contact opening is filled with a conductive plug.  
   
   
       76 . The processor-based system of  claim 75  wherein said conductive plug is a capacitor bottom electrode.  
   
   
       77 . The processor-based system of  claim 72  wherein said first and second conductive studs are connected to respective source and drain regions of a transistor.  
   
   
       78 . The processor-based system of  claim 77  wherein said first conductive stud is between wordline gates and said second conductive stud is between a wordline gate and an isolation gate.  
   
   
       79 . The processor-based system of  claim 77  wherein said source and drain regions are of an access transistor of a memory cell.  
   
   
       80 . The processor-based system of  claim 72  wherein said second conductive stud is a capacitor stud of a memory cell.  
   
   
       81 . An embedded-memory processor-based system, comprising: 
 a processor; and    a memory circuit formed on a same integrated circuit as said processor, wherein said memory circuit includes a memory device comprising:    a first conductive stud and a second conductive stud;    a bit line over and in electrical contact with said first conductive stud, wherein said bit line is overlying a portion of said second conductive stud; and    an insulating material separating said bit line from said second conductive stud, wherein said insulating material forms a sidewall surrounding a plug to said conductive stud.    
   
   
       82 . The embedded-memory processor-based system of  claim 81  wherein said first conductive stud has a silicide cap and said second contact stud does not have a silicide cap.  
   
   
       83 . The embedded-memory processor-based system of  claim 81  wherein said sidewalls within a contact opening containing said plug, wherein said contact opening is through an insulating layer which is over and around said bit line.  
   
   
       84 . The embedded-memory processor-based system of  claim 81  wherein said contact opening is filled with a conductive plug.  
   
   
       85 . The embedded-memory processor-based system of  claim 84  wherein said conductive plug is a capacitor bottom electrode.  
   
   
       86 . The embedded-memory processor-based system of  claim 81  wherein said first and second conductive studs are connected to respective source and drain regions of a transistor.  
   
   
       87 . The embedded-memory processor-based system of  claim 86  wherein said first conductive stud is between wordline gates and said second conductive stud is between a wordline gate and an isolation gate.  
   
   
       88 . The embedded-memory processor-based system of  claim 86  wherein said source and drain regions are of an access transistor of a memory cell.  
   
   
       89 . The embedded-memory processor-based system of  claim 81  wherein said second conductive stud is a capacitor stud of a memory cell.