Low voltage drive ferroelectric capacitor

Abstract

A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.

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       12 . An integrated circuit including: 
 a ferroelectric capacitor, comprising: 
 a bottom electrode formed over a substrate;  
 a ferroelectric and platinum thin film nanocomposite dielectric layer formed over said bottom electrode, wherein said nanocomposite layer includes nanoparticles of platinum; and  
 a top electrode formed over said dielectric layer.  
   
   
   
       13 . The integrated circuit of  claim 12 , wherein at least said bottom electrode includes a LaNiO 3  layer.  
   
   
       14 . The integrated circuit of  claim 12 , wherein said dielectric layer is a PZT-platinum thin film.  
   
   
       15 . The integrated circuit of  claim 14 , wherein said PZT-platinum thin film is less than approximately 10% platinum.  
   
   
       16 . The integrated circuit of  claim 12 , wherein said dielectric layer has a thickness of less than approximately 2000 Å.  
   
   
       17 . The integrated circuit of  claim 12 , wherein said ferroelectric capacitor is formed over a CMOS structure formed on said substrate.  
   
   
       18 . The integrated circuit of  claim 12 , wherein substantially all of said platinum nanoparticles have dimensions less than about 30 nm.  
   
   
       19 . The integrated circuit of  claim 12 , wherein said top and bottom electrodes each include a LaNiO 3  layer.  
   
   
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       25 . An integrated circuit including a ferroelectric memory device, comprising: 
 a substrate having formed thereon a plurality of address transistors;    a plurality of ferroelectric capacitors each formed over a respective one of said address transistors, each of said capacitors including: 
 a bottom electrode formed over said substrate;  
 a dielectric layer including a ferroelectric and platinum thin film formed over said bottom electrode, wherein said nanocomposite layer includes nanoparticles of platinum; and  
 a top electrode formed over said dielectric layer.  
   
   
   
       26 . The integrated circuit of  claim 25 , wherein said bottom electrode includes a layer LaNiO 3 .  
   
   
       27 . The integrated circuit of  claim 25 , wherein said dielectric layer is a PZT-platinum thin film.  
   
   
       28 . The integrated circuit of  claim 27 , wherein said PZT-platinum thin film is less than approximately 10% platinum.  
   
   
       29 . The integrated circuit of  claim 27 , wherein said dielectric layer has a thickness of less than approximately 2000 Å.  
   
   
       30 . The integrated circuit of  claim 27 , wherein substantially all of said platinum nanoparticles have dimensions less than about 30 nm.  
   
   
       31 . An integrated circuit including a plurality of ferroelectric capacitors each ferroelectric capacitor comprising: 
 a bottom electrode including a LaNiO 3  layer formed over a layer of platinum;    a dielectric layer including a ferroelectric and platinum thin film formed over said bottom electrode, wherein said nanocomposite layer includes nanoparticles of platinum; and    a top electrode including a layer of platinum formed over said dielectric layer.    
   
   
       32 . The integrated circuit of  claim 31 , wherein the top electrode of each capacitor further comprises a LaNiO 3  layer formed between said platinum layer and said dielectric layer.  
   
   
       33 . The integrated circuit of  claim 32 , wherein said dielectric layer has a thickness of less than approximately 2000 Å and wherein substantially all of said platinum nanoparticles have dimensions less than about 30 nm.  
   
   
       34 . The integrated circuit of  claim 33 , wherein said bottom electrode is formed over a layer of titanium.  
   
   
       35 . The integrated circuit of  claim 31 , wherein said dielectric layer has a thickness of less than approximately 2000 Å and wherein substantially all of said platinum nanoparticles have dimensions less than about 30 nm.  
   
   
       36 . The integrated circuit of  claim 35 , wherein said bottom electrode is formed over a layer of titanium.  
   
   
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