Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory

Abstract

A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.

1 . A non-volatile semiconductor memory comprising memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.  
     
     
         2 . The non-volatile semiconductor memory of  claim 1 , further comprising an enhancement mode select gate transistor connected to a source region of one of the memory cell transistors at one end of an array of the memory cell transistors arranded in a column direction of the matrix.  
     
     
         3 . The non-volatile semiconductor memory of  claim 1 , further comprising an enhancement mode select gate transistor connected to a drain region of one of the memory cell transistors at one end of an array of the memory cell transistors arranded in a column direction of the matrix.  
     
     
         4 . A non-volatile semiconductor memory having a plurality of memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor comprising: 
 source and drain regions having a first conductivity type disposed on an insulating layer;    a channel region having the first conductivity type disposed between the source and drain regions, and having a lower impurity concentration than the source and drain regions;    a floating gate electrode disposed above the channel region and insulated from the channel region; and    a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode.    
     
     
         5 . The non-volatile semiconductor memory of  claim 4 , wherein a plurality of the source regions, the channel regions and the drain regions are extended in a column direction on the matrix so as to implement an array of memory cell transistors, sharing each of the drain regions with one of the source regions in a pair of the memory cell transistors adjacent to each other in the array, and the source regions, the channel regions and the drain regions arranged in a subject column are isolated respectively from the source regions, the channel regions and the drain regions of the memory cell transistors arranged in a column adjacent to the subject column.  
     
     
         6 . The non-volatile semiconductor memory of  claim 4 , further comprising a semiconductor substrate disposed under the insulating layer.  
     
     
         7 . The non-volatile semiconductor memory of  claim 4 , further comprising a select gate transistor comprising: 
 a second drain region having the first conductivity type common to a source region of one of the memory cell transistors at one end of the memory cell transistors arranged in a column direction of the matrix so as to implement an array;    a channel region having a second conductivity type adjacent to the second drain region;    a second source region having the first conductivity type adjacent to the second channel region; and    a select gate electrode disposed above the second conductivity type channel region and insulated from the second channel region.    
     
     
         8 . The non-volatile semiconductor memory of  claim 7 , further comprising a source line contact being contacted with the second source region.  
     
     
         9 . The non-volatile semiconductor memory of  claim 4 , further comprising a select gate transistor comprising: 
 a second source region having the first conductivity type common to a drain region of one of the memory cell transistors at one end of the memory cell transistors arranged in column direction of the matrix so as to implement an array;    a second channel region having a second conductivity type adjacent to the second drain region;    a second drain region having the first conductivity type adjacent to the second channel region; and    a select gate electrode disposed above the second channel region and insulated from the second channel region.    
     
     
         10 . The non-volatile semiconductor memory of  claim 9 , further comprising a bit line contact being contacted with the second drain region.  
     
     
         11 . The non-volatile semiconductor memory of  claim 5 , further comprising an element isolation insulating film isolating a plurality of the source regions, the channel regions and the drain regions from each other in respective column direction.  
     
     
         12 . The non-volatile semiconductor memory of  claim 6 , further comprising a peripheral circuit disposed on the semiconductor substrate outside of a cell array comprising the memory cell transistors.  
     
     
         13 . The non-volatile semiconductor memory of  claim 6 , wherein the semiconductor substrate comprises a peripheral convex portion contacting the peripheral circuit through an opening disposed in the insulating layer.  
     
     
         14 . The non-volatile semiconductor memory of  claim 8 , wherein the semiconductor substrate comprises a convex cell array portion contacting with the second source region through an opening disposed in the insulating layer.  
     
     
         15 . A method for fabricating a non-volatile semiconductor memory comprising, forming a depletion mode memory cell transistor, comprising: 
 depositing a gate insulating film on a semiconductor layer having a first conductivity type disposed on an insulating layer;    depositing a floating gate electrode on the gate insulating film;    depositing an inter-electrode insulating film on the floating gate electrode;    depositing a control gate electrode on the inter-electrode insulating film;    forming a groove penetrating the control gate electrode, the inter-electrode insulating film and the floating gate electrode; and    forming source and drain regions having the first conductivity type in the semiconductor layer under the groove.    
     
     
         16 . The method of  claim 15 , further comprising forming enhancement mode select gate transistor, comprising: 
 forming an impurity diffusion having a second conductivity type layer in the semiconductor layer;    forming a select gate electrode on the impurity diffusion layer through the gate insulating film; and    forming second source and drain regions having the first type conductivity type in the impurity diffusion layer using the select gate electrode as a mask in a self-aligned manner.    
     
     
         17 . The method of  claim 15 , further comprising: 
 forming a peripheral convex portion from a part of the semiconductor substrate by removing a part of the semiconductor substrate selectively, before forming the semiconductor layer; and    removing a part of the insulating layer so as to expose the peripheral convex portion.    
     
     
         18 . The method of  claim 17 , wherein forming the semiconductor layer comprises depositing the semiconductor layer on the insulating layer and the peripheral convex portion.  
     
     
         19 . The method of  claim 18 , further comprising: 
 removing a part of the semiconductor layer so as to expose the peripheral convex portion; and    forming a peripheral circuit on the peripheral convex portion.    
     
     
         20 . The method of  claim 18 , further comprising: 
 forming a convex cell array portion from a part of the semiconductor substrate by removing a part of the semiconductor substrate selectively, before forming the semiconductor layer;    removing a part of the insulating layer so as to expose the convex cell array portion; and    forming a source line contact on the semiconductor layer directly above the convex cell array portion.