Semiconductor integrated circuit device

Abstract

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micropatterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

1 . A semiconductor memory device comprising: 
 first and second bit line:    a plurality of word lines;    a plurality of memory cells, each having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being coupled to an output terminal of said first inverter and with an output terminal being coupled to an input terminal of said first inverter, a third    N-channel MOS transistor having a source/drain path coupled between the output terminal of said first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of said second inverter and the second bit line, and each being connected to each of said plurality of word lines through said third N-channel MOS transistor;    a first P-type well region in which said first and third N-channel MOS transistors are formed commonly throughout said plurality of memory cells, said first P-type well region having a first diffusion layer;    a second P-type well region in which said second and fourth N-channel MOS transistors are formed commonly throughout said plurality of memory cells, said second P-type well region having a second diffusion layer; and    an N-type well region in which said first and second P-channel MOS transistors are formed commonly throughout said plurality of memory cells, said N-type well region lying between said first and second P-type well regions,    wherein said first diffusion layer formed in said first P-type well region in one of two memory cells is separated from said second diffusion layer formed in said second P-type well region in the other of the two memory cells which lies adjacently in a direction parallel to said plurality of word lines, and    wherein a ground voltage line is shared between the two memory cells and lies on a boundary of the two memory cells.    
   
   
       2 . The semiconductor memory device according to  claim 1 , further comprising: 
 a first electrical lead to supply a first voltage to said first and second P-type well regions; and    a second electrical lead to supply a second voltage to said N-type well region,    wherein said first and second electrical leads are common throughout said plurality of memory cells and lie parallel to said plurality of word lines.    
   
   
       3 . The semiconductor memory device according to  claim 2 , 
 wherein said first and second electrical leads are formed in another layer than a layer in which said first and second bit lines are formed in.    
   
   
       4 . The semiconductor memory device according to  claim 3 , 
 wherein said first and second electrical leads and said plurality of word lines are formed in a common layer each other.    
   
   
       5 . The semiconductor memory device according to  claim 2 , 
 wherein in case that said first and second P-type well regions are shared between two memory cells lying in a direction parallel to said plurality of word lines, said N-type well region is unshared between any of two memory cells lying in a direction parallel to said plurality of word lines, and    wherein in case that said first and second P-type well regions are unshared between any of two memory cells lying in a direction parallel to said plurality of word lines, said N-type well region is shared between two memory cells lying in a direction parallel to said plurality of word lines.    
   
   
       6 . The semiconductor memory device according to  claim 5 , wherein said first N-channel MOS transistor formed in one of said two memory cells lying in the direction parallel to said plurality of word lines is separated from said fourth N-channel MOS transistor formed in the other of said two memory cells lying in the direction parallel to said plurality of word lines, and 
 wherein said third N-channel MOS transistor formed in one of said two memory cells lying in the direction parallel to said plurality of word lines is separated from said second N-channel MOS transistor formed in the other of said two memory cells lying in the direction parallel to said plurality of word lines.    
   
   
       7 . The semiconductor memory device according to  claim 6 , wherein said first, second, third, and fourth N-channel MOS transistors formed in said plurality of memory cells lie in a direction parallel to a boundary of said first P-type well region and said N-type well region.  
   
   
       8 . The semiconductor memory device according to  claim 7 , wherein the first P-type well region includes a diffusion layer, 
 wherein an outer shape of the diffusion layer, defined by an isolation layer which extends along the entirety of each of the longitudinal sides of the diffusion layer, is substantially linearly symmetric relative to a line extending in a first direction through said P-type well region, and wherein the boundary of said first P-type well region and said N-type well region extends in said first direction.    
   
   
       9 . The semiconductor memory device according to  claim 7 , wherein said outer shape of the diffusion layer in the first P-type well is a rectangle.  
   
   
       10 . The semiconductor memory device according to  claim 7 , wherein said outer shape of the diffusion layer in the first P-type well is an outer shape of a combination of rectangles.  
   
   
       11 . The semiconductor memory device according to  claim 2 , wherein said first bit line lies between a first power supply line and a first ground line, and 
 wherein said second bit line lies between said first power supply line and a second ground line, and    wherein said first ground line is coupled to the source of said first N-channel MOS transistor and said second ground line is coupled to the source of said second N-channel MOS transistor.