Method of communicating between modules in a decoding system

Abstract

Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

1 . A decoding system comprising: 
 a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface; and    an entropy decoding accelerator coupled to the co-processor interface of the core decoder processor, wherein the entropy decoding accelerator is adapted to receive commands from the core decoder processor via the co-processor interface and to perform entropy decoding operations on entropy-coded code in the data stream in response to said commands.    
   
   
       2 . The system of  claim 1  wherein the core decoder processor is adapted to issue commands to the variable-length decoding accelerator and wherein the variable-length decoding accelerator is adapted to provide a command status signal to the core decoder processor, wherein the command status signal indicates whether or not a command is completed.  
   
   
       3 . The system of  claim 2  wherein the entropy decoding accelerator comprises a command status register that indicates whether or not a command is completed and wherein the core decoder processor is adapted to poll the command status register to determine if the command is completed.  
   
   
       4 . The system of  claim 3  wherein the core decoder processor does not issue a new command to the entropy decoder accelerator unless the command status register indicates that a previous command is completed.  
   
   
       5 - 6 . (canceled)  
   
   
       7 . The system of  claim 1  wherein the core decoder processor is adapted to perform decoding functions on a coded media data stream and the entropy decoding accelerator is adapted to perform entropy decoding operations on entropy-coded code in the media data stream.  
   
   
       8 . The system of  claim 1  wherein the core decoder processor is adapted to perform decoding functions on a coded video data stream and the entropy decoding accelerator is adapted to perform entropy decoding operations on entropy-coded code in the video data stream.  
   
   
       9 . A method of controlling a decoding accelerator, comprising: 
 (a) providing a command to the accelerator via a posted write operation; and    (b) polling the accelerator to determine whether an operation corresponding to the command has been performed.    
   
   
       10 . The method of  claim 9  wherein the decoding accelerator is coupled to a core decoder processor adapted to decode a data stream and wherein the decoding accelerator is adapted to assist the core decoder processor with a decoding function, wherein providing step (a) comprises providing, with the core decoder processor, a command to the accelerator via a posted write operation, and polling step (b) comprises polling the accelerator with the core decoder processor to determine whether the operation corresponding to the command has been performed.  
   
   
       11 . The method of  claim 10  wherein the command provided to the accelerator by the core decoder processor instructs the accelerator to perform the decoding function and wherein polling step (b) comprises polling the accelerator with the core decoder processor to determine whether the decoding function has been completed.  
   
   
       12 . The method of  claim 10  further comprising a step (c), performed after providing step (a) and prior to polling step (b), of performing a second decoding function with the core decoder processor.  
   
   
       13 . The method of  claim 10  wherein providing step (a) comprises: 
 (a)(i) providing the command to an intermediate storage element; and    (a)(ii) writing the command to the accelerator when the accelerator is ready to receive the command.    
   
   
       14 . The method of  claim 13  wherein step (a)(iii) is performed a plurality of core decoder clock cycles after step (a)(i) is performed.  
   
   
       15 . The method of  claim 10  further comprising a step (c), after step (b), of: 
 (c) after the core decoder processor determines, via its polling of the accelerator, that the operation corresponding to the command has been performed, providing, with the core decoder processor, a second command to the accelerator via a posted write operation.    
   
   
       16 - 18 . (canceled)  
   
   
       19 . A decoding system comprising: 
 a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; and    a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the first decoding accelerator is adapted to provide status data indicative of a status of the first accelerator to the co-processor status register; and    a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register.    
   
   
       20 . The system of  claim 19  wherein the core decoder processor is adapted to issue commands to the first and second decoding accelerators and wherein the first and second decoding accelerators are adapted to provide status data indicative of whether a command is completed to the co-processor status register.  
   
   
       21 . The system of  claim 19  further comprising: 
 a third decoding accelerator adapted to assist the core decoder processor with a third decoding function, wherein the third decoding accelerator is adapted to provide status data indicative of a status of the third accelerator to the co-processor status register.    
   
   
       22 - 26 . (canceled)  
   
   
       27 . The decoding system of  claim 1  wherein the entropy decoding accelerator is a variable-length decoding accelerator adapted to perform variable-length decoding operations on variable-length code in the data stream in response to said commands.  
   
   
       28 . The decoding system of  claim 1  wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on single-syntax elements in the data stream in response to said commands.  
   
   
       29 . The decoding system of  claim 1  wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on complete blocks of syntax elements in the data stream in response to said commands.  
   
   
       30 . The decoding system of  claim 1  wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on single-syntax elements and on complete blocks of syntax elements in the data stream in response to said commands.  
   
   
       31 . The decoding system of  claim 29  wherein the entropy decoding accelerator is adapted to concurrently perform entropy decoding operations on single-syntax elements and complete blocks of single-syntax elements in the data stream in response to said commands.