Multi-core debugger

Abstract

In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.

1 . A multi-core processor comprising: 
 a plurality of independent processor cores, each processor core executing instructions and operating in parallel to perform work;    each of the plurality of independent processor cores respectively including: 
 an interrupt-signal sensor; and  
 an interrupt-signal generator selectively providing an interrupt signal; and  
   a global interrupt-signal interconnect in electrical communication with each of the plurality of independent processor cores, more than one of the processor cores respectively interrupting its execution of instructions substantially simultaneously responsive to sampling with respective interrupt-signal sensors an interrupt signal on the global interrupt-signal interconnect.    
     
     
         2 . The multi-core processor of  claim 1 , wherein the respective interrupt-signal generator of each of the plurality of independent processor cores is coupled to the global interrupt-signal interconnect.  
     
     
         3 . The multi-core processor of  claim 2 , wherein the respective interrupt-signal generator of each of the plurality of independent processor cores is coupled to the global interrupt-signal interconnect in a wired-OR configuration.  
     
     
         4 . The multi-core processor of  claim 1 , wherein an interrupt signal is provided in response to a write to a register in one of the plurality of independent processor cores.  
     
     
         5 . The multi-core processor of  claim 1 , wherein an interrupt signal is provided in response to execution of a debug breakpoint instruction in one of the plurality of independent processor cores.  
     
     
         6 . The multi-core processor of  claim 1 , wherein an interrupt signal is provided in response to detection of an instruction or data breakpoint match in one of the plurality of independent processor cores.  
     
     
         7 . The multi-core processor of  claim 1 , wherein the global interrupt-signal interconnect comprises a plurality of independent global interrupt-signal interconnects, each of the independent global interrupt-signal interconnects representing a respective interrupt signal.  
     
     
         8 . The multi-core processor of  claim 1 , further comprising a trace buffer coupled to the global interrupt-signal interconnect, the trace buffer being configured to monitor memory transactions of the independent processor cores in response to an interrupt signal on the global interrupt-signal interconnect.  
     
     
         9 . The multi-core processor of  claim 1 , wherein each of the plurality of independent processor cores comprises a respective register storing information, the register configurable according to the sampled interrupt signal.  
     
     
         10 . The multi-core processor of  claim 1 , further comprising a core-processor clock signal for coordinating execution of the instructions, wherein the interrupt-signal sensor samples the global interrupt-signal interconnect during each cycle of the core-processor clock signal.  
     
     
         11 . The multi-core processor of  claim 10 , wherein each processor core respectively interrupts its execution of instructions within three core-processor clock cycles of sampling an interrupt signal on the global interrupt-signal interconnect.  
     
     
         12 . The multi-core processor of  claim 1 , wherein the global interrupt-signal interconnect is used to communicate after the plurality of processor cores are interrupted.  
     
     
         13 . A method of debugging a multi-core processor comprising the steps of: 
 selectively providing an interrupt signal on a global interrupt-signal interconnect, the global interrupt-signal interconnect coupled to each of a plurality of processor cores comprising the multi-core processor;    sampling the provided interrupt signal at each of the plurality of processor cores; and    interrupting execution of more than one of the plurality of processor cores substantially simultaneously responsive to the sensed interrupt signal.    
     
     
         14 . The method of  claim 13 , wherein the interrupt signal is selectively provided by one of the plurality of processor cores.  
     
     
         15 . The method of  claim 14 , wherein the interrupt signal is provided in response to software control.  
     
     
         16 . The method of  claim 15 , wherein the software control comprises software writing a value to a register.  
     
     
         17 . The method of  claim 14 , wherein the interrupt signal is provided in response to execution of a debug breakpoint instruction.  
     
     
         18 . The method of  claim 14 , wherein the interrupt signal is provided in response to a breakpoint match.  
     
     
         19 . The method of  claim 13 , further comprising entering a debug handler routine at each of the interrupted processor cores.  
     
     
         20 . The method of  claim 19 , wherein each of the interrupted processor cores communicates with an external device responsive to entering the debug handler routine.  
     
     
         21 . The method of  claim 20 , wherein each of the plurality of processor cores communicates with the external device using a Joint Test Action Group (JTAG) test access port.  
     
     
         22 . The method of  claim 20 , further comprising using the global interrupt-signal interconnect to communicate after the plurality of processor cores are interrupted.  
     
     
         23 . A multi-core processor comprising: 
 means for selectively providing an interrupt signal on a global interrupt-signal interconnect, the global interrupt-signal interconnect coupled to each of a plurality of processor cores comprising the multi-core processor;    means for sensing the provided interrupt signal at each of the plurality of processor cores; and    means for interrupting execution of more than one of the plurality of processors substantially simultaneously responsive to a sensed interrupt signal.