Method and apparatus for managing write back cache

Abstract

A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and 10 units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.

1 . A network services processor comprising: 
 a plurality of processors;    a coherent shared memory including a cache and a memory, the coherent shared memory shared by the plurality of processors; and    an input/output bridge coupled to the plurality of processors and the cache, the input/output bridge monitoring requests to free a buffer in memory to avoid writing a modified cache block in the cache back to the buffer.    
     
     
         2 . The network services processor of  claim 1 , wherein upon detecting a request to free the buffer, the input/output bridge issues a command to clear a dirty bit associated with the cache block.  
     
     
         3 . The network services processor of  claim 2  further comprising: 
 a cache controller coupled to the plurality of processors, the cache and the input/output bridge, the cache controller storing the dirty bit associated with the block and clearing the dirty bit upon receiving the command from the input/output bridge.    
     
     
         4 . The network services processor of  claim 3  wherein the input/output bridge further comprises: 
 a don't write back queue which stores commands to be issued to the cache controller.    
     
     
         5 . The network services processor of  claim 4  wherein the input/output bridge further comprises: 
 a free queue that stores requests to free blocks to be added to a free pool.    
     
     
         6 . The network services processor of  claim 5  further comprising: 
 a plurality of processing units coupled to the input/output bridge, the input/output bridge storing packets to be transferred between processing units and the coherent shared memory in which packets are stored for processing by the processors.    
     
     
         7 . The network services processor of  claim 1 , further comprising: 
 a memory allocator which provides free lists of buffers in memory for storing received packets.    
     
     
         8 . The network services processor of  claim 1 , wherein the coherent shared memory is coupled to the processors and input/output bridge by a coherent memory bus that includes a commit bus, a store bus, a fill bus and an add bus.  
     
     
         9 . A method for increasing memory bandwidth comprising: 
 sharing a coherent shared memory among a plurality of processors, the coherent shared memory including a cache and a memory; and    monitoring requests to free a buffer in memory to avoid writing a modified cache block in the cache back to the buffer.    
     
     
         10 . The method of  claim 9  further comprising: 
 upon detecting a request to free the buffer, issuing a command to clear a dirty bit associated with the cache block.    
     
     
         11 . The method of  claim 10  further comprising: 
 storing commands to be issued to the cache controller in a don't write back queue.    
     
     
         12 . The method of  claim 10  further comprising: 
 storing requests to free blocks to be added to a free pool in a free queue.    
     
     
         13 . The method of  claim 10  further comprising: 
 storing packets to be transferred between a plurality of processing units and the coherent shared memory in which packets are stored for processing by the processors.    
     
     
         14 . The method of  claim 9 , further comprising: 
 providing a list of free buffers in memory for storing received packets.    
     
     
         15 . The method of  claim 9 , wherein the coherent shared memory is coupled to the processors and input/output bridge by a coherent memory bus that includes a commit bus, a store bus, a fill bus and an add bus.  
     
     
         16 . A network services processor comprising: 
 means for sharing, by a plurality of processors a coherent shared memory, the coherent shared memory including a cache and a memory; and    means for monitoring requests to free a buffer in memory to avoid writing a modified cache block in the cache back to the buffer.    
     
     
         17 . A system for managing a write back cache comprising: 
 a memory; and    logic which issues a don't write back command in response to a request to free a buffer in the memory, the don't write back command issued to clear a dirty bit in a cache block associated with the buffer to avoid writing the modified cache block back to the buffer.