Inventor · disambiguated record
David Asher
Also filed as: ASHER DAVID · ASHER DAVID H · ASHER DAVID HOWARD
44 granted patents·3 pending applications·533 citations·filing 1998–2023
98Inventor score
Files withCAVIUM INC12MARVELL ASIA PTE LTD9CAVIUM LLC7HEWLETT PACKARD DEVELOPMENT CO7CAVIUM NETWORKS INC2
Top patents by PatentIndex Score
47 records- 0194US6633960B1Scalable directory based cache coherence protocolHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Oct 14, 2003·88 cites·32 claims
- 0293US10282299B2Managing cache partitions based on cache usage informationCAVIUM LLC·Filed 2017·Granted May 7, 2019·11 cites·20 claims
- 0392US10558573B1Methods and systems for distributing memory requestsCAVIUM LLC·Filed 2018·Granted Feb 11, 2020·6 cites·22 claims
- 0490US6681295B1Fast lane prefetchingHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jan 20, 2004·70 cites·17 claims
- 0588US11615027B2Methods and systems for distributing memory requestsMARVELL ASIA PTE LTD·Filed 2021·Granted Mar 28, 2023·1 cites·20 claims
- 0688US11036643B1Mid-level instruction cacheMARVELL ASIA PTE LTD·Filed 2019·Granted Jun 15, 2021·5 cites·12 claims
- 0788US7213087B1Mechanism to control the allocation of an N-source shared bufferHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted May 1, 2007·60 cites·22 claims
- 0886US11093405B1Shared mid-level data cacheMARVELL ASIA PTE LTD·Filed 2019·Granted Aug 17, 2021·3 cites·14 claims
- 0984US10331500B2Managing fairness for lock and unlock operations using operation prioritizationCAVIUM LLC·Filed 2017·Granted Jun 25, 2019·4 cites·32 claims
- 1084US8595401B2Input output bridgingCAVIUM INC·Filed 2013·Granted Nov 26, 2013·6 cites·22 claims
- 1184US6671822B1Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cacheHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Dec 30, 2003·36 cites·6 claims
- 1284US6654858B1Method for reducing directory writes and latency in a high performance, directory-based, coherency protocolHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 25, 2003·42 cites·18 claims
- 1381US11188466B2Methods and systems for distributing memory requestsMARVELL ASIA PTE LTD·Filed 2020·Granted Nov 30, 2021·1 cites·24 claims
- 1481US11119929B2Low latency inter-chip communication mechanism in multi-chip processing systemCAVIUM LLC·Filed 2019·Granted Sep 14, 2021·2 cites·20 claims
- 1581US10248420B2Managing lock and unlock operations using active spinningCAVIUM LLC·Filed 2017·Granted Apr 2, 2019·2 cites·20 claims
- 1681US9870328B2Managing buffered communication between coresCAVIUM INC·Filed 2014·Granted Jan 16, 2018·6 cites·12 claims
- 1780US9501425B2Translation lookaside buffer managementCAVIUM INC·Filed 2014·Granted Nov 22, 2016·6 cites·26 claims
- 1879US9372800B2Inter-chip interconnect protocol for a multi-chip systemCAVIUM INC·Filed 2014·Granted Jun 21, 2016·5 cites·24 claims
- 1979US9355206B2System and method for automated functional coverage generation and management for IC design protocolsCAVIUM INC·Filed 2014·Granted May 31, 2016·6 cites·19 claims
- 2078US11868262B2Methods and systems for distributing memory requestsMARVELL ASIA PTE LTD·Filed 2023·Granted Jan 9, 2024·0 cites·20 claims
- 2178US9141548B2Method and apparatus for managing write back cacheCAVIUM INC·Filed 2014·Granted Sep 22, 2015·3 cites·12 claims
- 2278US8473658B2Input output bridgingSANZONE ROBERT A·Filed 2011·Granted Jun 25, 2013·6 cites·22 claims
- 2376US10007614B2Method and apparatus for determining metric for selective cachingCAVIUM INC·Filed 2016·Granted Jun 26, 2018·2 cites·26 claims
- 2475US12019552B2Low latency inter-chip communication mechanism in a multi-chip processing systemMARVELL ASIA PTE LTD·Filed 2023·Granted Jun 25, 2024·0 cites·20 claims
- 2575US10002218B2Verification of a multichip coherence protocolCAVIUM INC·Filed 2016·Granted Jun 19, 2018·2 cites·33 claims
- 2675US7941585B2Local scratchpad and data caching systemCAVIUM NETWORKS INC·Filed 2004·Granted May 10, 2011·14 cites·20 claims
- 2772US9665505B2Managing buffered communication between socketsCAVIUM INC·Filed 2014·Granted May 30, 2017·3 cites·16 claims
- 2872US7606998B2Store instruction ordering for multi-core processorCAVIUM NETWORKS INC·Filed 2004·Granted Oct 20, 2009·19 cites·19 claims
- 2971US9612934B2Network processor with distributed trace buffersDOBBIE BRADLEY D·Filed 2011·Granted Apr 4, 2017·4 cites·12 claims
- 3071US9390023B2Method and apparatus for conditional storing of data using a compare-and-swap based approachCAVIUM INC·Filed 2013·Granted Jul 12, 2016·3 cites·21 claims
- 3171US9058463B1Systems and methods for specifying. modeling, implementing and verifying IC design protocolsCAVIUM INC·Filed 2014·Granted Jun 16, 2015·3 cites·29 claims
- 3269US11620223B2Low latency inter-chip communication mechanism in a multi-chip processing systemMARVELL ASIA PTE LTD·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 3367US6918015B2Scalable directory based cache coherence protocolHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jul 12, 2005·10 cites·15 claims
- 3466US12210457B1Processor data cache with shared mid-level cache and low-level cacheMARVELL ASIA PTE LTD·Filed 2021·Granted Jan 28, 2025·0 cites·17 claims
- 3563US9026312B2Ergonomics test buckSMITH TODD BARTHOLOMEW·Filed 2012·Granted May 5, 2015·5 cites·18 claims
- 3660US6212493B1Profile directed simulation used to target time-critical crossproducts during random vector testingCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 3, 2001·39 cites·21 claims
- 3760US6148427AMethod and apparatus for test data generationCOMPAQ COMPUTER CORP·Filed 1998·Granted Nov 14, 2000·34 cites·33 claims
- 3859US9330002B2Multi-core interconnect in a network processorKESSLER RICHARD E·Filed 2011·Granted May 3, 2016·1 cites·8 claims
- 3958US10599430B2Managing lock and unlock operations using operation predictionCAVIUM LLC·Filed 2017·Granted Mar 24, 2020·0 cites·20 claims
- 4058US10445096B2Managing lock and unlock operations using traffic prioritizationCAVIUM LLC·Filed 2017·Granted Oct 15, 2019·0 cites·20 claims
- 4156US5878054AMethod and apparatus for test data generationDIGITAL EQUIPMENT CORP·Filed 1998·Granted Mar 2, 1999·18 cites·21 claims
- 4253US7370151B2Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cacheHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted May 6, 2008·7 cites·18 claims
- 4352US11379379B1Differential cache block sizing for computing systemsMARVELL ASIA PTE LTD·Filed 2020·Granted Jul 5, 2022·0 cites·23 claims
- 4449US2006059316A1Method and apparatus for managing write back cacheCAVIUM NETWORKS·Filed 2005·Application pending·0 cites
- 4549US2015228199A1Ergonomics Test BuckCATERPILLAR INC·Filed 2015·Application pending·0 cites
- 4647US11327759B2Managing low-level instructions and core interactions in multi-core processorsMARVELL INT LTD·Filed 2018·Granted May 10, 2022·0 cites·24 claims
- 4744US2015254182A1Multi-core network processor interconnect with multi-node connectionCAVIUM INC·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →