Processor condition sensing circuits, systems and methods

Abstract

A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.

1 . A data processing device comprising: 
 a semiconductor chip;    an electronic processor on-chip; and    an on-chip condition sensor connected to said electronic processor for analysis of the operations thereof.    
   
   
       2 . The device of  claim 1  wherein said on-chip condition sensor includes a program address breakpoint circuit.  
   
   
       3 . The device of  claim 1  wherein said on-chip condition sensor includes a data address breakpoint circuit.  
   
   
       4 . The device of  claim 1  wherein said electronic processor includes a program counter, and said on-chip condition sensor includes a trace stack connected to said program counter.  
   
   
       5 . The device of  claim 4  wherein said on-chip condition sensor includes a trace stack-full sensor.  
   
   
       6 . The device of  claim 1  wherein said on-chip condition sensor includes a plurality of sensor circuits responsive to particular internal conditions of said electronic processor and sensor circuit selection circuitry.  
   
   
       7 . The device of  claim 6  wherein said sensor circuit selection circuitry includes a logic network connected to said sensor circuits and a serial scan circuit interconnected with said logic network for determining selections of sensor circuits by said logic network.  
   
   
       8 . The device of  claim 6  wherein said on-chip condition sensor includes a counter connectable to said sensor circuits.  
   
   
       9 . The device of  claim 8  wherein said on-chip condition sensor further includes a serial scan circuit interconnected with said counter for loading said counter with a value indicative of a predetermined count to which said condition sensor is thereby made sensitive.  
   
   
       10 . The device of  claim 8  wherein said on-chip condition sensor further includes a serial scan circuit, and a multiplexer having inputs connected to said sensor circuits and an output connected to said counter, the multiplexer making a selection responsive to said serial scan circuit.  
   
   
       11 . The device of  claim 1  wherein said on-chip condition sensor includes a sensor circuit responsive to an internal condition of said electronic processor and a counter connected to said sensor circuit.  
   
   
       12 . The device of  claim 1  wherein said on-chip condition sensor includes a sense circuit responsive to an interrupt.  
   
   
       13 . The device of  claim 1  wherein said on-chip condition sensor includes a sensor responsive to a subroutine call.  
   
   
       14 . The device of  claim 1  wherein said on-chip condition sensor includes a sensor responsive to a return transition.  
   
   
       15 . The device of  claim 1  wherein said on-chip condition sensor includes a sensor responsive to an instruction acquisition by said processor.  
   
   
       16 . The device of  claim 1  wherein said electronic processor includes a pipeline controller and said on-chip condition sensor is connected to said pipeline controller.  
   
   
       17 . The device of  claim 1  wherein said on-chip condition sensor is further coupled to said electronic processor to stop its operations upon sensing an occurrence of a predetermined condition.  
   
   
       18 . An electronic system comprising: 
 a data processing device including a semiconductor chip and an electronic processor on-chip; and    a host computer external to said chip and connected to said data processing device, said host computer having a speed of operation which is slower than said electronic processor, said data processing device further comprising an on-chip condition sensor coupled to said host computer and connected to stop said electronic processor automatically upon occurrence of a predetermined condition of operation of said data processing device.    
   
   
       19 . The electronic system of  claim 18  wherein said data processing device includes a serial scan circuit interconnected with said on-chip condition sensor and coupling said on-chip condition sensor to said host computer.  
   
   
       20 . The electronic system of  claim 18  wherein said electronic processor comprises a digital signal processor.  
   
   
       21 . The electronic system of  claim 18  wherein said on-chip condition sensor includes a hardware program address breakpoint circuit, the system further comprising a read-only memory addressable by a program address to which said hardware breakpoint circuit is sensitive.  
   
   
       22 . The electronic system of  claim 21  wherein said read-only memory is on-chip.  
   
   
       23 . The electronic system of  claim 18  wherein said data processing device includes a random access memory and a data address bus connected to said memory, and said on-chip condition sensor includes a hardware data address breakpoint circuit connected to said data address bus for data address breakpoint signaling.  
   
   
       24 . The electronic system of  claim 23  wherein said electronic processor is connected to said data address bus and said hardware breakpoint circuit includes a register for holding a reference address for comparison with addresses asserted by said electronic processor on said data address bus.  
   
   
       25 . The electronic system of  claim 23  wherein said electronic processor is connected to said data address bus and said hardware breakpoint circuit includes a register for holding a digital value representing a range of addresses for comparison with addresses asserted by said electronic processor on said data address bus.  
   
   
       26 . The electronic system of  claim 25  wherein said register holds a set of most significant bits of an address, thereby representing a range of addresses.  
   
   
       27 . The electronic system of  claim 18  wherein said on-chip condition sensor includes a plurality of sensor circuits responsive to particular internal conditions of said electronic processor, a logic network connected to said sensor circuits, and a serial scan circuit supplied with command bits by said host computer and interconnected with said logic network for determining selections of sensor circuits by said logic network.  
   
   
       28 . The electronic system of  claim 18  wherein said on-chip condition sensor includes sensor circuits responsive to particular internal conditions of said electronic processor, a counter connectable to said sensor circuits, and a serial scan circuit interconnected with said counter for loading said counter from said host computer with a value indicative of a predetermined count to which said condition sensor is thereby made sensitive.  
   
   
       29 . A method of controlling, by a host computer, operations of an electronic processor fabricated on a semiconductor chip and having a speed exceeding the speed of the host computer and seemingly incompatible with control by the host computer, the method comprising the steps of: 
 loading an on-chip condition sensor from the host computer with information at a lower speed of the host computer to establish the function desired of the on-chip condition sensor; and    sensing the operations of the electronic processor with the on-chip condition sensor, wherein the on chip condition sensor performs the established function at a speed compatible with the speed of the electronic processor.    
   
   
       30 . The method of  claim 29  further comprising the step of using the on-chip condition sensor to signal at a speed compatible with the speed of the electronic processor to make the electronic processor stop upon occurrence of a predetermined condition in the operations of the electronic processor, the predetermined condition being established by the loading step.  
   
   
       31 . The method of  claim 29  wherein the sensing step includes counting occurrences of selected conditions of the electronic processor and producing a signal when a predetermined count is reached.  
   
   
       32 . A data processing device comprising: 
 a program counter; and    program counter trace stack means for holding a predetermined number of addresses defining a history of address discontinuities in operation of said program counter.    
   
   
       33 . The data processing device of  claim 32  further comprising an externally accessible serial scan circuit interconnected with said program counter trace stack.  
   
   
       34 . The data processing device of  claim 32  further comprising a program counter stack.  
   
   
       35 . The data processing device of  claim 32  further comprising means for storing a state vector representing whether a particular address in said program counter trace stack means is a beginning or ending address of a discontinuity.  
   
   
       36 . The data processing device of  claim 32  wherein said program counter trace stack means includes means for recording how many entries have been pushed onto the stack.  
   
   
       37 . The data processing device of  claim 32  further comprising means connected to said program counter trace stack for producing a signal indicating when the stack is full.  
   
   
       38 . The data processing device of  claim 32  wherein said trace stack has entries pushable thereon and storage elements for extra bits for the entries, the data processing device further comprising an overflow signal producing element having an input and an output, a signal combining circuit having a first input connected to one of the storage elements and a second input and an output respectively connected to the output and input of the overflow signal producing element.  
   
   
       39 . The data processing device of  claim 32  further comprising a program memory connected to said program counter, an instruction decoder connected to said program memory, and an electronic adding and multiplying circuit connected to said instruction decoder.  
   
   
       40 . The data processing device of  claim 32  wherein the address discontinuities include discontinuities resulting from external interrupts.  
   
   
       41 . A method of monitoring operations of a data processing device having an electronic processor fabricated on a semiconductor chip, the method comprising the steps of: 
 sensing the operations of the electronic processor with a program counter trace stack on-chip that has a speed of operation compatible with the speed of the electronic processor; and    transferring the contents of the program counter trace stack by serial scan-out to a host computer at a slower rate compatible with the speed of the host computer for monitoring purposes.    
   
   
       42 . A data processing device comprising: 
 a program counter, a program counter stack, a trace stack and means for causing the program counter to count through a series of addresses; and    a control circuit for entering a jump address into said program counter in substitution for a current address in the series, thereby establishing a discontinuity, said control circuit including means for pushing the current address onto the program counter stack and the jump address onto the trace stack.    
   
   
       43 . The data processing device of  claim 42  wherein said control circuit includes means for pushing the current address onto the trace stack also.  
   
   
       44 . The data processing device of  claim 42  further comprising an interrupt circuit connected to said control circuit and memory means for storing an interrupt routine, said control circuit responsive to the memory means and comprising means also operative upon completion of the interrupt routine for popping the program counter stack and pushing the trace stack.  
   
   
       45 . The data processing device of  claim 44  wherein, upon completion of the interrupt routine, the trace stack is pushed with a most recently accessed address of the interrupt routine and a return address from which operations were interrupted.  
   
   
       46 . An electronic system comprising: 
 a data processing device including a semiconductor chip and an electronic processor on-chip; and    a host computer off-chip and coupled to said data processing device, said host computer having a speed of operation which is slower than said electronic processor, said data processing device further comprising an on-chip trace stack, and a stack-full signaling circuit having an input connected to said trace stack.    
   
   
       47 . The electronic system of  claim 46  wherein said electronic processor comprises a digital signal processor.  
   
   
       48 . The electronic system of  claim 46  wherein said data processing device includes a serial scan circuit interconnected with said electronic processor and said on-chip trace stack.  
   
   
       49 . The electronic system of  claim 46  wherein said electronic processor includes a program counter and control circuit means for pushing onto said trace stack at least two addresses defining a discontinuity in execution by said electronic processor.  
   
   
       50 . The electronic system of  claim 46  further comprising an on-chip program counter stack means for holding at least one address from which execution has been interrupted until operations return.  
   
   
       51 . The electronic system of  claim 46  further comprising means for storing respective bits corresponding to entries in said on-chip trace stack and representing whether each entry is a beginning or ending address of a discontinuity.  
   
   
       52 . A method of tracing operations of a data processing device having a program counter and program counter stack and a circuit for making the counter count through a continuous series of addresses and a circuit for entering a jump address into the program counter in substitution for a current address in the series, the method comprising the steps of: 
 pushing the latest address onto the program counter stack and pushing the new address onto a separate trace stack.    
   
   
       53 . The method of  claim 52  further comprising the steps of returning to the series of addresses, popping the program counter stack and pushing the trace stack.  
   
   
       54 . The method of  claim 52  wherein the data processing device is on a semiconductor chip and the separate trace stack is provided on the same semiconductor chip thereby allowing trace stack operations to be as fast as the operations of the rest of the data processing device.