Structure and method of high performance two layer ball grid array substrate

Abstract

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.

1 - 22 . (canceled)  
   
   
       23 . A computer-implemented method for modeling a high-performance, high I/O ball grid array substrate, intended for integrated circuit flip-chip assembly and having a first and a second metal layer and one intermediate insulating layer, all of substantially equal areas comprising the steps of: 
 modeling the structure of said first metal layer as electrical ground potential, said layer having a plurality of electrically insulated openings for electrical contacts;    modeling the structure of said second metal layer as a plurality of electrical signal lines, a plurality of first electrical power lines operable at a first potential, and a plurality of second electrical power lines operable at a second potential;    configuring said first power lines so wide that their combined inductances approximate the inductance of a metal having the size of the total substrate;    concurrently distributing said first power lines among said signal lines in order to provide at least minimum inductive coupling between signal and power lines, thereby obtaining high mutual inductances and minimizing effective self-inductance;    
   
   
       24 - 29 . (canceled)  
   
   
       30 . A method of fabricating a packaged integrated circuit, comprising the steps of: 
 providing a substrate having first and second opposing surfaces;    providing a plurality of signal lines, a plurality of first power lines coupleable to a first power source, and a plurality of second power lines coupleable to a second power source, all on said second surface, at least one of said plurality of signal lines disposed between a pair of said plurality of first power lines, and said signal lines between said pair of said plurality of first power lines and said pair of said plurality of first power lines disposed between a pair of said second power lines; and    providing an integrated circuit chip mounted on said substrate.    
   
   
       31 . The method of  claim 30 , further including providing said signal lines of a first width, said first power lines of a second width different from said first, and said second power lines of a third width different from said first and second widths.  
   
   
       32 . The method of  claim 31 , wherein said third width is wider than said second width, and said second width is wider than said first width.  
   
   
       33 . The method of  claim 30 , further including the step of providing a ground plane on said first surface of said substrate.  
   
   
       34 . A method of fabricating a packaged integrated circuit, comprising the steps of: 
 providing a substrate having first and second opposing surfaces, said substrate having thereon:    providing a plurality of groups of lines, said plurality of groups of lines including groups of lines of at least three different widths disposed on said second surface of said substrate, said groups of lines arranged such that one or more lines in a first group of lines of a first width are disposed between lines of a second group of lines of a second width and lines in said second group of lines of said second width are disposed between lines of said third width; and    providing an integrated circuit chip;    mounting said chip on said substrate; and    coupling said chip to at least some of said lines.    
   
   
       35 . The method of  claim 34 , wherein said lines of said first width are signal lines, said lines of said second width are power lines coupled to a first voltage potential, and said lines of said third width are power lines coupled to a second voltage potential.  
   
   
       36 . The method of  claim 34 , further comprising the step of providing a ground plane on said first surface of said substrate.