US2006066335A1PendingUtilityA1

Semiconductor test device with heating circuit

35
Individually held — no corporate assignee on recordPriority: Sep 28, 2004Filed: Sep 28, 2004Published: Mar 30, 2006
Est. expirySep 28, 2024(expired)· nominal 20-yr term from priority
Inventors:Seung H. KangSubramanian KarthikeyanSailesh Mansinh MerchantLisa Mullin
G01R 31/2877G01R 31/2856
35
PatentIndex Score
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Claims

Abstract

A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

Claims

exact text as granted — not AI-modified
1 . A semiconductor test device comprising: 
 a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit; and    a heating circuit, integrally formed with the semiconductor test device, comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.    
   
   
       2 . The semiconductor test device of  claim 1 , wherein the meander of the heating circuit is oriented parallel with a plane of the test circuit.  
   
   
       3 . The semiconductor test device of  claim 2 , wherein the heating circuit is positioned to be coplanar with the test circuit.  
   
   
       4 . The semiconductor test device of  claim 2 , wherein the heating circuit surrounds a periphery of the test circuit.  
   
   
       5 . The semiconductor test device of  claim 2 , wherein the wafer comprises at least two layers, the heating circuit being positioned in a first layer and the test circuit being positioned in a second layer.  
   
   
       6 . The semiconductor test device of  claim 5 , wherein the heating circuit surrounds a periphery of the test circuit projected onto the first layer.  
   
   
       7 . The semiconductor test device of  claim 6 , wherein the heating circuit overlaps a periphery of the test circuit projected onto the first layer.  
   
   
       8 . The semiconductor test device of  claim 2 , wherein the wafer comprises at least three layers, a first portion of the heating circuit being positioned in a first layer, the test circuit being positioned in a second layer below the first layer, and a second portion of the heating circuit being positioned in a third layer below the second layer.  
   
   
       9 . The semiconductor test device of  claim 8 , wherein the heating circuit surrounds a periphery of the test circuit projected into the first layer.  
   
   
       10 . The semiconductor test device of  claim 9 , wherein the heating circuit overlaps a periphery of the test circuit projected into the first layer.  
   
   
       11 . The semiconductor test device of  claim 8 , wherein the second heating circuit surrounds a periphery of the test circuit projected into the third layer.  
   
   
       12 . The semiconductor test device of  claim 11 , wherein the second heating circuit overlaps a periphery of the test circuit projected into the third layer.  
   
   
       13 . The semiconductor test device of  claim 1 , the heating circuit comprising a plurality of meanders, wherein at least a first portion of the meanders of the heating circuit are oriented vertically with respect to a horizontal plane of the test circuit.  
   
   
       14 . The semiconductor test device of  claim 13 , wherein the at least some of the first portion of the meanders surrounds a periphery of the test circuit.  
   
   
       15 . The semiconductor test device of  claim 13 , wherein the semiconductor test device comprises at least three layers, the test circuit being positioned in a second layer between a first layer and third layer, the at least some of the first portion of the meanders being positioned in the three layers so that the at least some of the first portion of meanders extend into the first, second, and third layers.  
   
   
       16 . The semiconductor test device of  claim 15 , wherein the heating circuit surrounds the periphery of the test circuit.  
   
   
       17 . The semiconductor test device of  claim 15 , wherein the heating circuit further comprises a second plurality of meanders positioned in the first layer and oriented parallel with the plane of the test circuit.  
   
   
       18 . The semiconductor test device of  claim 15 , wherein the second plurality of meanders covers a periphery of the test circuit projected onto the first layer.  
   
   
       19 . The semiconductor test device of  claim 15 , wherein the heating circuit further comprises a third plurality of meanders positioned in the third layer and oriented parallel with the plane of the test circuit.  
   
   
       20 . The semiconductor test device of  claim 15 , wherein the third plurality of meanders covers a periphery of the test circuit projected onto the third layer.  
   
   
       21 . The semiconductor test device of  claim 1 , wherein the heating circuit receives an alternating current heating signal from a heating circuit controller.  
   
   
       22 . The semiconductor test device of  claim 21 , wherein the alternating current is turned on and off to expose the test circuit to temperature cycling at a rate corresponding to the rate at which the alternating current is turned on and off.  
   
   
       23 . The semiconductor test device of  claim 1 , wherein the heating circuit comprises a heating conductor trace having a trace width and trace height approximately the same as a trace width and trace height of a conductor trace in the test circuit.  
   
   
       24 . The semiconductor test device of  claim 1  further comprising a plurality of circuit meanders positioned around the test circuit to enclose the test circuit within a space defined by the plurality of circuit meanders.  
   
   
       25 . A semiconductor test device comprising: 
 a plurality of test die having contacts for applying an electrical signal and measuring electrical parameters of the test die; and    a plurality of heating circuits, each heating circuit associated with a respective test die, each heating circuit integrally formed within the semiconductor test device and comprising at least one circuit meander positioned adjacent the respective test die for raising a temperature of the respective test die.    
   
   
       26 . A method for evaluating reliability in a test circuit of a semiconductor device comprising: 
 integrally forming a heating circuit comprising a circuit meander positioned adjacent a test circuit in the semiconductor device;    applying an alternating current to the heating circuit to induce heating of the heating circuit; and    measuring an electrical parameter of the test circuit responsive to the heating of the heating circuit.    
   
   
       27 . The method of  claim 26 , further comprising turning the alternating current on and off to expose the test circuit to temperature cycling at a rate corresponding to the rate at which the alternating current is turned on and off.

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