US2006075296A1PendingUtilityA1

Method, apparatus and system for data integrity of state retentive elements under low power modes

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Individually held — no corporate assignee on recordPriority: Sep 30, 2004Filed: Sep 30, 2004Published: Apr 6, 2006
Est. expirySep 30, 2024(expired)· nominal 20-yr term from priority
Inventors:Sankaran M. MenonThomas J. Mozdzen
G06F 11/1012
45
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Claims

Abstract

In some embodiments, a method, apparatus and system for data integrity of state retentive elements under low power modes are generally presented. In this regard, an integrity agent is introduced to generate one or more error checking bits for content within a logic block in response to an indication associated with a request to enter a low power mode. Other embodiments are also disclosed and claimed.

Claims

exact text as granted — not AI-modified
1 . A method comprising: 
 generating one or more error checking bits for content within a logic block in response to an indication associated with a request to enter a low power mode.    
   
   
       2 . The method of  claim 1 , further comprising: 
 utilizing the error checking bits after resuming from the low power mode to determine if an error has occurred.    
   
   
       3 . The method of  claim 2 , further comprising: 
 correcting errors detected.    
   
   
       4 . The method of  claim 2 , further comprising: 
 reporting errors detected to a system error handler.    
   
   
       5 . The method of  claim 2 , wherein generating one or more error checking bits for content within a logic block comprises: 
 serially shifting content within the logic block into an error checking unit.    
   
   
       6 . The method of  claim 2 , wherein generating one or more error checking bits for content within a logic block comprises: performing serial and parallel exclusive or (XOR) functions on contents within the logic block.  
   
   
       7 . An electronic appliance, comprising: 
 one or more input/output (I/O) devices;    at least one logic block, coupled with the one or more I/O devices; and    an integrity engine coupled with the logic block, the integrity engine to generate one or more error checking bits for content within the logic block in response to an indication associated with a request to enter a low power mode.    
   
   
       8 . The electronic appliance of  claim 7 , further comprising: 
 the integrity engine to utilize the error checking bits after resuming from the low power mode to determine if an error has occurred.    
   
   
       9 . The electronic appliance of  claim 8 , further comprising: 
 the integrity engine to correct errors detected.    
   
   
       10 . The electronic appliance of  claim 8 , further comprising: 
 the integrity engine to report errors detected to a system error handler.    
   
   
       11 . A storage medium comprising content which, when executed by an accessing machine, causes the accessing machine to generate one or more error checking bits for content within a logic block in response to an indication associated with a request to enter a low power mode.  
   
   
       12 . The storage medium of  claim 11 , further comprising content which, when executed by the accessing machine, causes the accessing machine to utilize the error checking bits after resuming from the low power mode to determine if an error has occurred.  
   
   
       13 . The storage medium of  claim 12 , further comprising content which, when executed by the accessing machine, causes the accessing machine to correct single bit errors and to report double bit errors to a system error handler.  
   
   
       14 . The storage medium of  claim 13 , wherein the content to generate one or more error checking bits for content within a logic block comprises content which, when executed by the accessing machine, causes the accessing machine to perform serial and parallel exclusive or (XOR) functions on contents within the logic block.  
   
   
       15 . The storage medium of  claim 13 , wherein the content to generate one or more error checking bits for content within a logic block comprises content which, when executed by the accessing machine, causes the accessing machine to serially shift content within the logic block into an error checking unit.  
   
   
       16 . An apparatus, comprising: 
 a logic block; and    circuitry coupled with the logic block, the circuitry to generate and store one or more error checking bits for content within the logic block in response to an indication associated with a request to enter a low power mode.    
   
   
       17 . The apparatus of  claim 16 , wherein the circuitry to generate one or more error checking bits comprises circuitry to serially shift content within the logic block into an error checking unit.  
   
   
       18 . The apparatus of  claim 17 , further comprising circuitry to correct single bit errors and detect double bit errors.  
   
   
       19 . The apparatus of  claim 16 , wherein the circuitry to generate one or more error checking bits comprises circuitry to generate serial and parallel error checking bits for contents within the logic block.  
   
   
       20 . The apparatus of  claim 19 , further comprising circuitry to correct single bit errors and detect double bit errors.  
   
   
       21 . The apparatus of  claim 16 , wherein the circuitry to generate one or more error checking bits comprises circuitry to generate serial error checking bits for rows of contents within the logic block.  
   
   
       22 . The apparatus of  claim 16 , wherein the circuitry to generate one or more error checking bits comprises circuitry to generate parallel error checking bits for columns of contents within the logic block.

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