Barrier enhancement process for copper interconnects

Abstract

A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10 Å to 100 Å and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

1 - 61 . (canceled)  
   
   
       62 . A process for applying a metal to a microelectronic work-piece, the microelectronic work-piece including a surface in which are disposed one or more micro-recessed structures, the process comprising: 
 (a) forming a barrier layer on the surface of the microelectronic work-piece, including on the walls of the micro-recessed structures;    (b) forming a barrier enhancement layer over the barrier layer, wherein said enhancement layer comprises a metal alloy selected from the group consisting of Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P and Co—W—P; and    (c) electroplating a metal onto the barrier enhancement layer so as to fill the micro-recessed structure.    
   
   
       63 . The process of  claim 62 , wherein the enhancement layer is formed using an electrochemical deposition process.  
   
   
       64 . The process of  claim 63 , wherein the electrochemical deposition process is selected from the group consisting of electroless and electroplating processes.  
   
   
       65 . The process of  claim 62 , wherein the enhancement layer is formed using a CVD process.  
   
   
       66 . The process of  claim 62 , wherein the enhancement layer is formed using a PVD process.  
   
   
       67 . The process of  claim 62 , wherein the enhancement layer is formed with a thickness of 100 Å or less.  
   
   
       68 . The process of  claim 62 , wherein the enhancement layer is formed with a thickness in the range of from 10 Å to 100 Å thick.  
   
   
       69 . The process of  claim 62 , wherein the barrier layer so formed has seams, discontinuities or grain boundary defects, and wherein the enhancement layer conformally covers the barrier layer.  
   
   
       70 . The process of  claim 62 , wherein the alloy is Co—P.  
   
   
       71 . The process of  claim 62 , wherein the alloy is Co—W—P.  
   
   
       72 . The process of  claim 62 , wherein the metal electroplated onto the enhancement layer is copper.  
   
   
       73 . The process of  claim 62 , further comprising: 
 (d) removing a portion of the metal from the surface of the microelectronic work-piece.    
   
   
       74 . The process of  claim 73 , wherein the removing is by chemical mechanical polishing.  
   
   
       75 . The process of  claim 62 , wherein the microelectronic work-piece is a silicon or gallium arsenide semiconductor wafer.  
   
   
       76 . A process for applying a metal to a microelectronic work-piece, the microelectronic work-piece including a surface in which are disposed one or more micro-recessed structures, the process comprising: 
 (a) forming a barrier layer on the surface of the microelectronic work-piece, including on the walls of the micro-recessed structures;    (b) forming a barrier enhancement layer of a metal alloy over the barrier layer, wherein said metal alloy is selected from the group consisting of Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P and Co—W—P;    (c) forming a seed layer over the enhancement layer; and    (d) electroplating a metal onto the seed layer so as to fill the micro-recessed structure.    
   
   
       77 . The process of  claim 76 , wherein the enhancement layer is formed using an electrochemical deposition process.  
   
   
       78 . The process of  claim 77 , wherein the electrochemical deposition process is selected from the group consisting of electroless and electroplating processes.  
   
   
       79 . The process of  claim 76 , wherein the enhancement layer is formed using a CVD process.  
   
   
       80 . The process of  claim 76 , wherein the enhancement layer is formed using a PVD process.  
   
   
       81 . The process of  claim 76 , wherein the enhancement layer is formed with a thickness of 100 Å or less.  
   
   
       82 . The process of  claim 76 , wherein the enhancement layer is formed with a thickness in the range of from 10 Å to 100 Å thick.  
   
   
       83 . The process of  claim 76 , wherein the barrier layer so formed has seams, discontinuities or grain boundary defects, and wherein the enhancement layer conformally covers the barrier layer.  
   
   
       84 . The process of  claim 76 , wherein the alloy is Co—P.  
   
   
       85 . The process of  claim 76 , wherein the alloy is Co—W—P.  
   
   
       86 . The process of  claim 76 , wherein the metal electroplated onto the enhancement layer is copper.  
   
   
       87 . The process of  claim 76 , further comprising: 
 (e) removing a portion of the metal from the surface of the microelectronic work-piece.    
   
   
       88 . The process of  claim 87 , wherein the removing is by chemical mechanical polishing.  
   
   
       89 . The process of  claim 76 , wherein the microelectronic work-piece is a silicon or gallium arsenide semiconductor wafer.