Variable mask field exposure

Abstract

A method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design. Each of the integrated circuits is formed with a plurality of layer patterns. At least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design. The first layer pattern is imaged on the substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon. No other layer patterns of the first layer patterns and the second layer patterns are formed on the first mask. The first number is less than the plurality of integrated circuits formed on the substrate. The first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the exposure tool. The first layer patterns on the first mask are formed at a size that is larger than a size at which the first layer patterns are imaged on the substrate. The second layer patterns are imaged on the substrate using an exposure tool and a second mask having a second number of the second layer patterns formed in a block thereon. At least one additional layer pattern of the second layer patterns is formed on the second mask. The second number is less than the plurality of integrated circuits formed on the substrate. The second layer patterns are imaged on the substrate by stepping and repeating the block of second number of second layer patterns across the substrate with the exposure tool. The second layer patterns on the second mask are formed at a size that is larger than a size at which the second layer patterns are imaged on the substrate.

1 . In a method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design, where each of the integrated circuits is formed with a plurality of layer patterns, where at least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design, the improvement comprising the steps of: 
 imaging the first layer pattern on the substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon, with no other layer patterns of the first layer patterns and the second layer patterns formed on the first mask, where the first number is less than the plurality of integrated circuits formed on the substrate, and the first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the exposure tool, and the first layer patterns on the first mask are formed at a size that is larger than a size at which the first layer patterns are imaged on the substrate, and    imaging the second layer pattern on the substrate using an exposure tool and a second mask having a second number of the second layer patterns formed in a block thereon, with at least one additional layer pattern of the second layer patterns formed on the second mask, where the second number is less than the plurality of integrated circuits formed on the substrate, and the second layer patterns are imaged on the substrate by exposing and repeating the block of second number of second layer patterns across the substrate with the exposure tool, and the second layer patterns on the second mask are formed at a size that is larger than a size at which the second layer patterns are imaged on the substrate.    
     
     
         2 . The method of  claim 1 , wherein the first number of first layer patterns is greater than the second number of second layer patterns.  
     
     
         3 . The method of  claim 1 , wherein the block of first number of first layer patterns is imaged using a wide field mode on the exposure tool.  
     
     
         4 . The method of  claim 1 , wherein the block of second number of second layer patterns is imaged using a narrow field mode on the exposure tool.  
     
     
         5 . The method of  claim 1 , wherein the second mask includes separate blocks of all second layer patterns required for the fabrication of the plurality of integrated circuits according to the first integrated circuit design.  
     
     
         6 . A mask set for a first integrated circuit design, the mask set comprising: 
 a first mask having only a block of a first number of first layer patterns of the first integrated circuit design, where the first number is less than the plurality of integrated circuits formed on the substrate, and the first layer patterns on the first mask are formed at a size that is larger than a size at which the first layer patterns are imaged on a substrate, and the first layer patterns are common between the first integrated circuit design and at least one other integrated circuit design, and    a second mask having a block of a second number of second layer patterns of the first integrated circuit design, where the second number is less than the plurality of integrated circuits formed on the substrate, and the second layer patterns on the second mask are formed at a size that is larger than a size at which the second layer patterns are imaged on the substrate, and the second layer patterns are unique to the first integrated circuit design,    the second mask also having a block of a third number of third layer patterns of the first integrated circuit design, where the third number is less than the plurality of integrated circuits formed on the substrate, and the third layer patterns on the second mask are formed at a size that is larger than a size at which the third layer patterns are imaged on the substrate, and the third layer patterns are unique to the first integrated circuit design.    
     
     
         7 . The mask set of  claim 6 , wherein the first number of first layer patterns is greater than the second number of second layer patterns.  
     
     
         8 . The mask set of  claim 6 , wherein the block of first number of first layer patterns is imaged using a wide field mode on the exposure tool.  
     
     
         9 . The mask set of  claim 6 , wherein the block of second number of second layer patterns is imaged using a narrow field mode on the exposure tool.  
     
     
         10 . The mask set of  claim 6 , wherein the second mask includes separate blocks of all unique layer patterns required for the first integrated circuit design.  
     
     
         11 . A method of imaging a family of related integrated circuit designs, where the family of related integrated circuit designs includes at least a first layer pattern in common between the family of related integrated circuit designs, and each of the integrated circuit designs within the family of related integrated circuit designs includes a least a second layer pattern that is unique to a given one of the integrated circuit designs within the family of related integrated circuit designs, the method comprising the steps of: 
 imaging the first layer pattern on a substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon, with no other layer patterns of the first layer patterns and the second layer patterns formed on the first mask, where the first number is less than a number of integrated circuits formed on the substrate, and the first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the stepper, and the first layer patterns on the first mask are formed at a size that is larger than a size at which the first layer patterns are imaged on the substrate, and    imaging the second layer pattern on the substrate using an exposure tool and a second mask having a second number of the second layer patterns formed in a block thereon, where the second number is less than the first number, with at least one additional layer pattern of the second layer patterns formed on the second mask, where the second number is less than the number of integrated circuits formed on the substrate, and the second layer patterns are imaged on the substrate by exposing and repeating the block of second number of second layer patterns across the substrate with the exposure tool, and the second layer patterns on the second mask are formed at a size that is larger than a size at which the second layer patterns are imaged on the substrate.    
     
     
         12 . The method of  claim 11 , wherein the first number of first layer patterns is greater than the second number of second layer patterns.  
     
     
         13 . The method of  claim 11 , wherein the block of first number of first layer patterns is imaged using a wide field mode on the exposure tool.  
     
     
         14 . The method of  claim 11 , wherein the block of second number of second layer patterns is imaged using a narrow field mode on the exposure tool.