Memory capable of storing information and the method of forming and operating the same

Abstract

The present invention discloses a method for manufacturing memory unit capable of storing multi-bits binary information. Firstly, a gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of the dielectric layer. Subsequently, a first oxide layer is conformally formed on the gate and the semiconductor substrate. An charge-trapping layer is conformally formed on the first oxide layer, and subsequently a second oxide layer is conformally formed on the isolating layer. Next, a second etching is performed to etch the second oxide layer and the charging-trapping layer to form sandwich spacers composed of the second oxide layer/the isolating layer/the first oxide layer on the substrate and the gate sidewall. An ion implantation is performed by using the gate and the spacers acting as a mask to form source/drain doped regions in the semiconductor substrate, wherein junctions of said substrate to said the source/drain doped regions locate right under said spacers. Finally, a metal silicide is formed on exposed surface of the gate and surface of the source/drain doped regions.

1 . A method for manufacturing a memory unit capable of storing single-bit or multi-bits information, said method comprising the steps of: 
 providing a substrate with a gate dielectric and gate structure formed thereon;    performing an optional pocket ion implantation by using said gate structure as a mask to form pocket doped regions nearby said gate edge in said substrate;    forming a first oxide layer over said gate structure;    forming a charge-trapping layer over said first oxide layer, and subsequently forming a second oxide layer over said charge-trapping layer;    performing an etching to etch said second oxide layer said charge-trapping layer and said first oxide layer to form sandwich spacers comprised of said second oxide layer/said charge-trapping layer/said first oxide layer on the sidewall of said gate structure;    performing an ion implantation by using said gate structure and said spacers as a mask to form source/drain doped regions in said substrate, wherein junctions of said substrate to said source/drain doped regions locate right under said spacers.    
   
   
       2 . The method of  claim 1 , wherein said dielectric layer includes gate oxide layer.  
   
   
       3 . The method of  claim 1 , wherein material of said gate includes doped polysilicon or doped epitaxial silicon or combination of metal suicides and doped polysilicon.  
   
   
       4 . The method of  claim 1 , wherein materials of said gate include combinations of metal silicides and doped polysilicon  
   
   
       5 . The method of  claim 1 , wherein said first oxide layer can be partially etched or optionally etched.  
   
   
       6 . The method of  claim 1 , wherein said first and said second oxide layer include SiO 2 , HfO 2 , ZrO 2  or dielectric layer having an energy gap greater than said charge-trapping layer.  
   
   
       7 . The method of  claim 4 , wherein said charge-trapping layer includes nitride layer or oxynitride layer or a dielectric layer having an energy gap smaller than said first and said second oxide layer.  
   
   
       8 . The method of  claim 1 , further comprising: 
 performing an etching to remove dielectrics on the surface of said gate structure and said source/drain doped regions and;    forming a metal silicide on exposed surface of said gate structure and said source/drain doped regions.    
   
   
       9 . The method of  claim 8 , wherein material of said metal silicide includes TiSi 2 , CoSi 2  or NiSi.  
   
   
       10 . A method of programming memory units capable of storing multi-bits information, said memory units having a gate, a first spacer formed on a first sidewall of said gate as a first memory unit, a second spacer formed on a second sidewall of said gate as a second memory unit, a first doped region and second doped region respectively formed in a semiconductor substrate adjacent to said gate, said method comprising: 
 applying a gate bias to said gate;    applying a drain bias to said first doped region while applying a predetermined source voltage or a predetermined source current to said second doped region, wherein hot carriers are generated near the junction of said first doped region and stored in said first spacer, said first memory unit being defined as digital zero, otherwise being defined as digital one; and    applying said drain bias to said second doped region while applying a predetermined source voltage or a predetermined source current to said first doped region wherein hot carriers are generated near the junction of said second doped region and stored in said second spacer, said second memory unit being defined as digital zero, otherwise being defined as digital one.    
   
   
       11 . The method of  claim 10 , further comprising: 
 erasing said memory units by exposing said memory units in UV environment.    
   
   
       12 . The method of  claim 10 , wherein said gate bias is greater than threshold voltage of said memory units.  
   
   
       13 . A method of erasing memory units capable of storing multi-bits information, said memory units having a gate, a first spacer formed on a first sidewall of said gate as a first memory unit, a second spacer formed on a second sidewall of said gate as a second memory unit, a first and second doped regions respectively formed in a semiconductor substrate adjacent to said gate, said method comprising: 
 applying a gate bias to said gate for erasing; and    applying a first erasing current or first erasing bias to said first doped region while applying a second erasing current or second erasing bias to said second doped region, such that hetero-carriers current is respectively generated between said first doped region and said first memory unit, said second doped region and second memory unit, thereby erasing said first and second memory units.    
   
   
       14 . A method of reading memory units capable of storing multi-bits information, said memory units having a gate, a first spacer formed on a first sidewall of said gate as a first memory unit, a second spacer formed on a second sidewall of said gate as a second memory unit, a first and second doped regions respectively formed in a semiconductor substrate adjacent to said gate, said method comprising: 
 applying said gate bias to said gate;    applying said drain bias to said second doped region while applying a ground or a predetermined voltage to said first doped region; wherein when a predetermined amount of channel carrier flow or greater amount is generated from said first doped region to said second doped region, said first memory unit being defined as digital one, otherwise digital zero;    applying said drain bias to said first doped regions while applying said a ground or a predetermined voltage to said second doped region; wherein when a predetermined amount of channel carrier flow or greater amount is generated from said second doped region to said first doped region, said second memory unit being defined as digital one, otherwise digital zero.    
   
   
       15 . The method of  claim 14 , wherein said gate bias is greater than threshold voltage of said memory units.  
   
   
       16 . A method of programming memory units capable of storing single-bit information, said memory units having a gate, a first spacer formed on a first sidewall of said gate as a first memory unit, a second spacer formed on a second sidewall of said gate as a second memory unit, a first doped region and second doped region respectively formed in a semiconductor substrate adjacent to said gate, said method comprising: 
 applying a gate bias to said gate;    applying a drain bias to said first doped region while applying a predetermined source voltage or a predetermined source current to said second doped region, wherein hot carriers are generated near the junction of said first doped region and stored in said first spacer, said first memory unit being defined as digital zero, otherwise being defined as digital one; and    
   
   
       17 . The method of  claim 16 , further comprising: 
 erasing said memory units by exposing said memory units in UV environment.    
   
   
       18 . The method of  claim 16 , wherein said gate bias is greater than threshold voltage of said memory units.  
   
   
       19 . A method of erasing memory units capable of storing single-bit information, said memory units having a gate, a first spacer formed on a first sidewall of said gate as a first memory unit, a second spacer formed on a second sidewall of said gate as a second memory unit, a first and second doped regions respectively formed in a semiconductor substrate adjacent to said gate, said method comprising: 
 applying a gate bias to said gate for erasing; and    applying a first erasing current or first erasing bias to said first doped region, such that hetero-carriers current is generated between said first doped region and said first memory unit, thereby erasing said first memory units.    
   
   
       20 . A method of reading memory units capable of storing single-bit information, said memory units having a gate, a first spacer formed on a first sidewall of said gate as a first memory unit, a second spacer formed on a second sidewall of said gate as a second memory unit, a first and second doped regions respectively formed in a semiconductor substrate adjacent to said gate, said method comprising: 
 applying said gate bias to said gate;    applying said drain bias to said second doped region while applying a ground or a predetermined voltage to said first doped region; wherein when a predetermined amount of channel carrier flow or greater amount is generated from said first doped region to said second doped region, said first memory unit being defined as digital one, otherwise digital zero;    
   
   
       21 . The method of  claim 20 , wherein said gate bias is greater than threshold voltage of said memory units.