Method and apparatus for using internal delays for adjusting setup and hold times in a memory device

Abstract

A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly within a the storage area of the memory device, so that the parasitic capacitance inherent within the address and control lines can be advantageously employed for introducing delay. The parasitic delay enables the clock, address, and control lines to be synchronized, yet does not require introducing delay blocks and so the overall speed of the memory device is improved.

1 - 25 . (canceled)  
   
   
       26 . A memory device, comprising: 
 an input buffer for receiving from a first signal line externally supplied information;    a core memory storage area connected to said input buffer through an internal signal line; and    a latch, located within said core memory storage area and connected to said signal line for latching said externally supplied information on said internal signal line in response to an externally supplied clock signal received on a clock signal line.    
   
   
       27 . The memory device of  claim 26 , wherein a predetermined timing relationship between said externally supplied clock signal and said externally supplied information is maintained at said latch by delaying said externally supplied information through a delay device.  
   
   
       28 . The memory device of  claim 27 , wherein said externally supplied information comprises address information.  
   
   
       29 . The memory device of  claim 28 , wherein said externally supplied information further comprises command information.  
   
   
       30 . The memory device of  claim 29 , wherein said externally supplied information further comprises data to be written to said core memory storage area.  
   
   
       31 . A memory device, comprising: 
 a plurality of address input buffers for receiving address data;    a core memory storage area;    a plurality of data input buffers for receiving data to be stored in said core memory storage area;    a first and second plurality of delay devices;    a plurality of address signal lines;    a plurality of data signal lines;    a plurality of address latches provided at said core memory storage area and respectively connected by said plurality of address signal lines and said first plurality of delay devices to said plurality of address input buffers;    a plurality of data latches provided at said memory core storage area and respectively connected by said plurality of data signal lines and said second plurality of delay devices to said plurality of data input buffers; and    a clock signal path for providing a clock signal for operating said latches to latch in incoming data;    wherein said clock signal, address data, and data to be stored are provided from an external source    
   
   
       32 . The memory device of  claim 31 , wherein a predetermined timing relationship between said clock signal and each of said address data and data to be stored is respectively maintained at said pluralities of address and data latches by said first and second plurality of delay devices.  
   
   
       33 . The memory device of  claim 32 , further comprising: 
 a plurality of command input buffers for receiving command data.    
   
   
       34 . A processor system, comprising: 
 a processor; and    a memory circuit for exchanging data with said processor, said memory circuit comprising a memory device, said memory device comprising:    an input buffer for receiving from a first signal line externally supplied information;    a core memory storage area connected to said input buffer through an internal signal line; and    a latch, located within said core memory storage area and connected to said signal line for latching said externally supplied information on said internal signal line in response to an externally supplied clock signal received on a clock signal line.    
   
   
       35 . The memory device of  claim 34 , wherein a predetermined timing relationship between said externally supplied clock signal and said externally supplied information is maintained at said latch by delaying said externally supplied information through a delay device.  
   
   
       36 . The memory device of  claim 35 , wherein said externally supplied information comprises address information.  
   
   
       37 . The memory device of  claim 36 , wherein said externally supplied information further comprises command information.  
   
   
       38 . The memory device of  claim 37 , wherein said externally supplied information further comprises data to be written to said core memory storage area.  
   
   
       39 . A method of operating a memory device, comprising: 
 transmitting, from an external source, a first signal via an input buffer to a memory core area along a first transmission path;    transmitting, from said external source, a clock signal in accordance with a predetermined timing relationship to said first signal, to said memory core area;    delaying the transmission said first signal along said first transmission path to maintain said predetermined timing relationship; and    latching said first signal into said memory core area with a latch located inside said memory core using said clock signal.