Integrated circuits with contemporaneously formed array electrodes and logic interconnects

Abstract

The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.

1 . A method of forming electrodes and interconnects for an integrated circuit memory device, the method comprising: 
 forming a first layer of metallization;    forming electrodes for a memory array from the first layer of metallization to form electrodes; and    forming interconnects for logic of the integrated circuits at the same time as forming electrodes and from the same first layer of metallization.    
   
   
       2 . The method as defined in  claim 1 , further comprising forming magnetic keepers for electrodes and interconnects.  
   
   
       3 . The method as defined in  claim 1 , further comprising: 
 forming a dielectric layer;    patterning the dielectric layer;    forming the first layer of metallization on the patterned dielectric layer; and    performing chemical-mechanical planarization to remove portions of the first layer of metallization from undesired areas.    
   
   
       4 . The method as defined in  claim 1 , further comprising: 
 forming a patterned mask over the first layer of metallization; and    etching to remove portions of the first layer of metallization from undesired areas.    
   
   
       5 . The method as defined in  claim 1 , wherein forming electrodes for the memory array further comprises forming electrodes at a first pitch, and wherein forming interconnects for logic comprises forming interconnects at a second pitch, where the second pitch is different from the first pitch.  
   
   
       6 . The method as defined in  claim 1 , wherein forming electrodes for the memory array further comprises forming electrodes at a first pitch, and wherein forming interconnects for logic comprises forming interconnects at a second pitch, where the second pitch is looser than the first pitch.