High performance CMOS devices and methods for making same

Abstract

An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

1 . A method of manufacturing an integrated circuit, the method comprising the steps of: 
 forming a gate structure over a substrate;    forming pocket implant regions and source/drain extensions in the substrate;    forming spacers along sides of the gate structure; and    thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature.    
   
   
       2 . The method according to  claim 1 , wherein the gate structure comprises a gate conductor composed of a material selected from the group consisting of poly-Si, poly SiGe, metal, metal oxide, metal nitride, silicide and combinations thereof.  
   
   
       3 . The method according to  claim 1 , wherein the ultra-low temperature is between about 350° C. and about 800° C.  
   
   
       4 . The method according to  claim 1 , wherein the thermal annealing step is performed for a time period of between about 5 seconds and about 700 minutes.  
   
   
       5 . An integrated circuit comprising: 
 a gate structure over a substrate;    pocket implant regions and source/drain extensions in the substrate; and    spacers disposed along sides of the gate structure, the spacers formed while thermal annealing the substrate at an ultra-low temperature.    
   
   
       6 . The integrated circuit according to  claim 5 , wherein the gate structure comprises a gate conductor composed of a material selected from the group consisting of poly-Si, poly SiGe, metal, metal oxide, metal nitride, silicide and combinations thereof.  
   
   
       7 . The integrated circuit according to  claim 5 , wherein the ultra-low temperature is between about 350° C. and about 800° C.  
   
   
       8 . The integrated circuit according to  claim 5 , wherein the thermal annealing step is performed for a time period of between about 5 seconds and about 700 minutes.  
   
   
       9 . A method of manufacturing an integrated circuit, the method comprising the steps of: 
 forming a gate structure over a substrate;    forming source/drain extensions in the substrate; and    performing a thermal cycle process for solid phase epitaxy on the substrate.    
   
   
       10 . The method according to  claim 9 , further comprising the step of thermal annealing the substrate at an ultra-low temperature.  
   
   
       11 . The method according to  claim 10 , wherein the ultra-low temperature is between about 350° C. and about 800° C.  
   
   
       12 . The method according to  claim 9 , further comprising the step of forming pocket implant regions in the substrate.  
   
   
       13 . The method according to  claim 12 , further comprising the step of thermal annealing the substrate at an ultra-low temperature.  
   
   
       14 . The method according to  claim 13 , wherein the ultra-low temperature is between about 350° C. and about 800° C.  
   
   
       15 . The method according to  claim 12 , wherein the step of forming pocket implant regions in the substrate is performed prior to the step of forming source/drain implant regions in the substrate.  
   
   
       16 . The method according to  claim 13 , wherein the thermal annealing step is performed after the step of forming the pocket implant regions and before the step of forming the source/drain extensions.  
   
   
       17 . The method according to  claim 10 , wherein the thermal annealing step is performed after the step of performing a thermal cycle process for solid phase epitaxy.  
   
   
       18 . A method of manufacturing an integrated circuit, the method comprising the steps of: 
 forming a gate structure over a substrate;    forming a super halo-shape pocket implant region in the substrate;    forming thin, off-set spacers along sides of the gate structure; and    forming source/drain extensions in the substrate.    
   
   
       19 . A method of manufacturing an integrated circuit, the method comprising the steps of: 
 forming a gate structure over a substrate;    forming pocket implant regions and source/drain extensions in the substrate;    forming spacers along sides of the gate structure;    performing a low dosage source/drain implant; and    performing a high dosage source/drain implant.    
   
   
       20 . The method according to  claim 19 , wherein the low dosage source/drain implant is performed at a high energy.  
   
   
       21 . The method according to  claim 20 , wherein the high energy comprises less than 150 kev.  
   
   
       22 . The method according to  claim 19 , wherein the low dosage source/drain implant is performed with a dopant dosage of less than 1E15 cm−2.  
   
   
       23 . The method according to  claim 22 , wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.  
   
   
       24 . The method according to  claim 19 , wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.  
   
   
       25 . An integrated circuit comprising: 
 a gate structure over a substrate;    pocket implant regions and source/drain extensions in the substrate; and    graded source/drain regions in the substrate, the graded source/drain regions formed by a low dosage source/drain implant and a high dosage source/drain implant.    
   
   
       26 . The integrated circuit according to  claim 25 , wherein the low dosage source/drain implant is performed at a high energy.  
   
   
       27 . The integrated circuit according to  claim 26 , wherein the high energy comprises less than 150 kev.  
   
   
       28 . The integrated circuit according to  claim 25 , wherein the low dosage source/drain implant is performed with a dopant dosage of less than 1E15 cm−2.  
   
   
       29 . The integrated circuit according to  claim 28 , wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.  
   
   
       30 . The integrated circuit according to  claim 25 , wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.  
   
   
       31 . An integrated circuit comprising: 
 a gate structure over a substrate;    a super halo-shape pocket implant region in the substrate;    thin, off-set spacers disposed along sides of the gate structure; and    source/drain extensions in the substrate.